| Resume alert | Resumes 61 - 70 of 191 |
Project Manager Design
Fullerton, CA
... In depth knowledge of flip-flops, transistors, registers, counters, transformers, FPGA, ADC/DCA, fiber optics communication, FETs, wireless communications and satellites. During my work I dealt with many electrical and electronic components like Op ... - 2018 Mar 06
... In depth knowledge of flip-flops, transistors, registers, counters, transformers, FPGA, ADC/DCA, fiber optics communication, FETs, wireless communications and satellites. During my work I dealt with many electrical and electronic components like Op ... - 2018 Mar 06
Manufacturing Engineer Project Manager
Huntington Park, CA
... for circuit simulations and performed DC and AC analysis of circuit to ensure consistency between design and implementation SKILLS: ● MATLAB, Simulink, VHDL, FPGA, Xilinx, Arduino Uno, PCB design, Assembly, JAVA, C, soldering ● Microsoft Office; ... - 2018 Feb 22
... for circuit simulations and performed DC and AC analysis of circuit to ensure consistency between design and implementation SKILLS: ● MATLAB, Simulink, VHDL, FPGA, Xilinx, Arduino Uno, PCB design, Assembly, JAVA, C, soldering ● Microsoft Office; ... - 2018 Feb 22
ASIC Design, VLSI, RTL, Computer Engineer
Los Angeles, CA
... Synthesized into gate cells with PCHB templates Music Visualizer Embedded System (SoC) Design, UD [Xilinx IDE, FPGA, EDK, SDK, VHDL, C, Python] February - May 2016 • Designed a Music Visualizer with VGA output prototyped on Spartan-6 FPGA board • ... - 2017 Dec 04
... Synthesized into gate cells with PCHB templates Music Visualizer Embedded System (SoC) Design, UD [Xilinx IDE, FPGA, EDK, SDK, VHDL, C, Python] February - May 2016 • Designed a Music Visualizer with VGA output prototyped on Spartan-6 FPGA board • ... - 2017 Dec 04
QA Manager
Garden Grove, CA
... Head of Software QA Engineering 08/2008 – 08/2009 Altera (Intel FPGA) •Ramped up software verification team for new Altera R&D center in Vietnam (Altera now is part of Intel) •Adopted/customized development, verification practices and processes. ... - 2017 Nov 16
... Head of Software QA Engineering 08/2008 – 08/2009 Altera (Intel FPGA) •Ramped up software verification team for new Altera R&D center in Vietnam (Altera now is part of Intel) •Adopted/customized development, verification practices and processes. ... - 2017 Nov 16
Computer Science System
Los Angeles, CA
... Object detection system implementation on FPGA board. ( 30 acceleration in processing speed after optimization ) Summer intern in the Center for Customizable Domain-Specific Computing, UCLA (2016.8 - 2016.9) Advisor: Professor Jason Cong (Area: ... - 2017 Nov 04
... Object detection system implementation on FPGA board. ( 30 acceleration in processing speed after optimization ) Summer intern in the Center for Customizable Domain-Specific Computing, UCLA (2016.8 - 2016.9) Advisor: Professor Jason Cong (Area: ... - 2017 Nov 04
Engineer Design
Torrance, CA
... CLPD, FPGA programming in Verilog HDL with Xilinx tools and work flow Electronics Engineer 09/04-04/07 Glentek, Inc., El Segundo, CA LabVIEW programming for ATE, Data Acquisition and Analysis, Measurement, Instrument Remote Control thru RS232 and ... - 2017 Oct 19
... CLPD, FPGA programming in Verilog HDL with Xilinx tools and work flow Electronics Engineer 09/04-04/07 Glentek, Inc., El Segundo, CA LabVIEW programming for ATE, Data Acquisition and Analysis, Measurement, Instrument Remote Control thru RS232 and ... - 2017 Oct 19
Design Electrical Engineering
Los Angeles, CA
... FPGA Prototyping of Bi-Drectional Counter [Tools: QuestaSim, Quatus-II] [June 2017] • A digital counter is synthesized on Altera Cyclone IV FPGA board. • STA and delay optimization is performed on the design. • Obtained 100% code coverage on RTL. ... - 2017 Sep 18
... FPGA Prototyping of Bi-Drectional Counter [Tools: QuestaSim, Quatus-II] [June 2017] • A digital counter is synthesized on Altera Cyclone IV FPGA board. • STA and delay optimization is performed on the design. • Obtained 100% code coverage on RTL. ... - 2017 Sep 18
Verilog, VHDL, Python, C, C#, PL/SQL
Los Angeles, CA
... Node: 45nm Tomasulo Processor (32 bit) with Out of Order execution, In Order Completion Summer 2016 Designed a 32 bit Out of Order Execution and In Order Completion Tomasulo Processor in VHDL and implemented on Nexys 4 Artix7 FPGA board. Implemented ... - 2017 Sep 15
... Node: 45nm Tomasulo Processor (32 bit) with Out of Order execution, In Order Completion Summer 2016 Designed a 32 bit Out of Order Execution and In Order Completion Tomasulo Processor in VHDL and implemented on Nexys 4 Artix7 FPGA board. Implemented ... - 2017 Sep 15
Design Electrical Engineering
Los Angeles, CA
... Nexys 4 Artix7 FPGA board. Implemented Re-Order Buffer (ROB) for in order completion, Copy Free Check pointing (CFC) and Free Register List (FRL) for usage of Register Alias Table (RAT). Designed Branch Prediction Buffer (BPB), Return Address Stack ... - 2017 Aug 17
... Nexys 4 Artix7 FPGA board. Implemented Re-Order Buffer (ROB) for in order completion, Copy Free Check pointing (CFC) and Free Register List (FRL) for usage of Register Alias Table (RAT). Designed Branch Prediction Buffer (BPB), Return Address Stack ... - 2017 Aug 17
Engineering Design
Fullerton, CA
... and Mumbai, Fullerton, Microprocessors, Microwave (INDIA RF/GPA: GPA: INDIA Mixed 78/Fullerton, 80/100 100 Engineering, Signal FPGA CA, IC design) design, USA RF engineering, GPA: Random 3.3 Signal VLSI Analysis, testing and communication design for ... - 2017 Aug 04
... and Mumbai, Fullerton, Microprocessors, Microwave (INDIA RF/GPA: GPA: INDIA Mixed 78/Fullerton, 80/100 100 Engineering, Signal FPGA CA, IC design) design, USA RF engineering, GPA: Random 3.3 Signal VLSI Analysis, testing and communication design for ... - 2017 Aug 04