| Resume alert | Resumes 71 - 80 of 419 |
Power Electrical
Vasant Nagar, Karnataka, India
... Description: Application of the Msp430 in place of FPGA to control the power requirements of a satellite. Centre: ISRO, U.R. Rao Satellite Centre. Achievements: Cleared GATE exam 2019 with a score of 414. Obtained an overall percentile of 81.68 in ... - 2019 Apr 16
... Description: Application of the Msp430 in place of FPGA to control the power requirements of a satellite. Centre: ISRO, U.R. Rao Satellite Centre. Achievements: Cleared GATE exam 2019 with a score of 414. Obtained an overall percentile of 81.68 in ... - 2019 Apr 16
Design Engineering
Vasant Nagar, Karnataka, India
... 10th cross #1/1, Mobile: +91-886******* Kothnur Post, Bengaluru-560077 LinkedIn ID ac81zv@r.postjobfree.com Summary of Qualifications Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. ... - 2019 Apr 10
... 10th cross #1/1, Mobile: +91-886******* Kothnur Post, Bengaluru-560077 LinkedIn ID ac81zv@r.postjobfree.com Summary of Qualifications Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. ... - 2019 Apr 10
Design Verification Engineer
Vasant Nagar, Karnataka, India
... VLSI Domain Skills: • HDL : Verilog • HVL : SystemVerilog • Verification Methodology : Coverage Driven Verification • TB Methodology : UVM • Protocols : SPI • EDA Tools : Riviera Pro – Aldec, ISE – Xilinx • Domain : ASIC/FPGA front-end Design and ... - 2019 Apr 05
... VLSI Domain Skills: • HDL : Verilog • HVL : SystemVerilog • Verification Methodology : Coverage Driven Verification • TB Methodology : UVM • Protocols : SPI • EDA Tools : Riviera Pro – Aldec, ISE – Xilinx • Domain : ASIC/FPGA front-end Design and ... - 2019 Apr 05
Training Design
Bangalore, Karnataka, India
RAMAYANAMTHARUNKUMAR MailId:tharun******@ac8ofy@r.postjobfree.com Mobileno:+91-773******* B.Tech(ECE) SkillSet HDLs Hardware Scripting Programming Tools Language Verilog, ZedBoard, TCL(basic) C(basic) QuestaSim, FPGA,SV Xilinx7series Vivado FPGA ... - 2019 Mar 05
RAMAYANAMTHARUNKUMAR MailId:tharun******@ac8ofy@r.postjobfree.com Mobileno:+91-773******* B.Tech(ECE) SkillSet HDLs Hardware Scripting Programming Tools Language Verilog, ZedBoard, TCL(basic) C(basic) QuestaSim, FPGA,SV Xilinx7series Vivado FPGA ... - 2019 Mar 05
Training Design
Bangalore, Karnataka, India
... Understanding knowledge in RTL coding (Verilog and VHDL) with FPGA Prototype. • Exposure to EDA Tools: Synopsis IC-Compiler. • Operating System and Programming Language: Windows, Unix, TCL, VHDL and Verilog. INTERNSHIP AND TRAINING: • Physical ... - 2019 Mar 05
... Understanding knowledge in RTL coding (Verilog and VHDL) with FPGA Prototype. • Exposure to EDA Tools: Synopsis IC-Compiler. • Operating System and Programming Language: Windows, Unix, TCL, VHDL and Verilog. INTERNSHIP AND TRAINING: • Physical ... - 2019 Mar 05
Engineer Project
Bangalore, Karnataka, India
... Roles&Responsibilities: Understanding various flow like VCS to XTOR and VCS to ZEBU flow, and tools involving in the flow for apply stimulus generated in SVTB to RTL present in FPGA. Writing SV based tests and converts them in V2VX and V2Z format to ... - 2019 Feb 18
... Roles&Responsibilities: Understanding various flow like VCS to XTOR and VCS to ZEBU flow, and tools involving in the flow for apply stimulus generated in SVTB to RTL present in FPGA. Writing SV based tests and converts them in V2VX and V2Z format to ... - 2019 Feb 18
Engineer Design
Bangalore, Karnataka, India
... Technical Areas of Interest Physical Design Verilog PCB Design FPGA ASIC Projects undergone Mini Projects Development and Analysis of State Variable Filter: --(Matlab) Design and Implementation of 4:16 Bit Decoder: --(VIRTUOSO) Development of FSM ... - 2018 Oct 29
... Technical Areas of Interest Physical Design Verilog PCB Design FPGA ASIC Projects undergone Mini Projects Development and Analysis of State Variable Filter: --(Matlab) Design and Implementation of 4:16 Bit Decoder: --(VIRTUOSO) Development of FSM ... - 2018 Oct 29
Power Plant Design
Bangalore, Karnataka, India
... Mini Projects OCT-DEC,2016 Initially,we started with module level project as Traffic Light Controller.Then as part of FPGA level project, I accomplished Boothe Multiplier,Universal Shift Register and Synchronous FIFO.These themes were also ... - 2018 Sep 24
... Mini Projects OCT-DEC,2016 Initially,we started with module level project as Traffic Light Controller.Then as part of FPGA level project, I accomplished Boothe Multiplier,Universal Shift Register and Synchronous FIFO.These themes were also ... - 2018 Sep 24
M.Tech fresher in VLSI system Design with 11 month internship in MBRDI
Bangalore, Karnataka, India
... Calculation of sine and cosine angles using cordic algorithm in Vivado using Verilog and implemention on FPGA : CORDIC algorithm is an efficient means of calculating trigonometric and hyperbolic functions. By using tangent of some angles, one can ... - 2018 Aug 11
... Calculation of sine and cosine angles using cordic algorithm in Vivado using Verilog and implemention on FPGA : CORDIC algorithm is an efficient means of calculating trigonometric and hyperbolic functions. By using tangent of some angles, one can ... - 2018 Aug 11
Embedded system Engineer
Bangalore, Karnataka, India
... Proteus Achievements /Seminars/Workshops: National Instruments :- “ RF/Microwave Design And Simulation Workshop” Seminar :- “Recent Trends In Fpga And Embedded System” Workshop :- “Arduino Workshop” Job Profile: Company :- Binary Lifestyle Pvt. ... - 2018 Jul 12
... Proteus Achievements /Seminars/Workshops: National Instruments :- “ RF/Microwave Design And Simulation Workshop” Seminar :- “Recent Trends In Fpga And Embedded System” Workshop :- “Arduino Workshop” Job Profile: Company :- Binary Lifestyle Pvt. ... - 2018 Jul 12