| Resume alert | Resumes 41 - 50 of 419 |
Python Engineering
Bangalore, Karnataka, India
... Also I have done hands on training on FPGA and also made an inverter using cadence tool. Position of Responsibility T&P Cell (Training and Placement Cell of NIT Sikkim) NIT Sikkim LEAD COORDINATOR May. 2019 - Present • T&P Cell is the most active ... - 2020 Oct 30
... Also I have done hands on training on FPGA and also made an inverter using cadence tool. Position of Responsibility T&P Cell (Training and Placement Cell of NIT Sikkim) NIT Sikkim LEAD COORDINATOR May. 2019 - Present • T&P Cell is the most active ... - 2020 Oct 30
Electronics and Communication Engineer, Fresher
CV Raman Nagar, Karnataka, India
... Workshop in ’FPGA-Firmware development in VLSI’ - 2020 Oct 09
... Workshop in ’FPGA-Firmware development in VLSI’ - 2020 Oct 09
Design Python
Bangalore, Karnataka, India
... Super Resolution of images on FPGA (Final project in process) Spatial Domain analysis of images for improvising the resolution of images. Creating Degradation models and then applying Super Resolution algorithms on Simulink and using Xilinx system ... - 2020 Oct 06
... Super Resolution of images on FPGA (Final project in process) Spatial Domain analysis of images for improvising the resolution of images. Creating Degradation models and then applying Super Resolution algorithms on Simulink and using Xilinx system ... - 2020 Oct 06
Engineering Project
Vasant Nagar, Karnataka, India
... • Attended workshop organised by ASICCENTRE OF EXCELLENCE on FPGA implementation of processing algorithms for digital images held on February 2018. • Participated in ESIM Circuit Simulation Project conducted by IIT BOMBAY “Design of clipper using ... - 2020 Sep 16
... • Attended workshop organised by ASICCENTRE OF EXCELLENCE on FPGA implementation of processing algorithms for digital images held on February 2018. • Participated in ESIM Circuit Simulation Project conducted by IIT BOMBAY “Design of clipper using ... - 2020 Sep 16
Engineer
Vasant Nagar, Karnataka, India
... • Worked on FPGA, Real Time, and Simulated Applications of LabVIEW. TETRA PAK INDIA PVT LTD, Pune, MH, IN Renovation Engineer Intern, July 2019 – Aug 2019 • Worked on Tetra Pak UHT packing machine manufacturing. • Manufacturing and Assembly of UHT ... - 2020 Aug 21
... • Worked on FPGA, Real Time, and Simulated Applications of LabVIEW. TETRA PAK INDIA PVT LTD, Pune, MH, IN Renovation Engineer Intern, July 2019 – Aug 2019 • Worked on Tetra Pak UHT packing machine manufacturing. • Manufacturing and Assembly of UHT ... - 2020 Aug 21
Manager Power
Bengaluru, Karnataka, India
... Validated the RTL netlist on Altera Quartus 2 boards (FPGA Boards) to check the correct functionality. Developed testcases for advertiser and scanner devices using BLE 5.0 protocol. Ensured that Code coverage and Functional Coverage of the BLE 5.0 ... - 2020 Jun 20
... Validated the RTL netlist on Altera Quartus 2 boards (FPGA Boards) to check the correct functionality. Developed testcases for advertiser and scanner devices using BLE 5.0 protocol. Ensured that Code coverage and Functional Coverage of the BLE 5.0 ... - 2020 Jun 20
Verilog, System Verilog, UVM, Digital Electronics, C, Perl, Python
Bangalore, Karnataka, India
... Centre for Development of Advanced Computing (C-DAC) Mohali Summer Intern June, 2018 – July, 2018 Worked on the major projects “UART Implementation” on Spartan 3 FPGA kit using VHDL. Worked on mini projects “Traffic Light Controller Implementation” ... - 2020 Apr 28
... Centre for Development of Advanced Computing (C-DAC) Mohali Summer Intern June, 2018 – July, 2018 Worked on the major projects “UART Implementation” on Spartan 3 FPGA kit using VHDL. Worked on mini projects “Traffic Light Controller Implementation” ... - 2020 Apr 28
Engineer Power
Vasant Nagar, Karnataka, India
... Implemented the digital sliding mode control by using FPGA, and compared the results with analog controller. B.E, Electrical and Electronics Engineering at, 2009-2013. B.V.B College of engineering, Hubli, Karnataka- 580031 Intermediate (+2), 2007 ... - 2020 Mar 02
... Implemented the digital sliding mode control by using FPGA, and compared the results with analog controller. B.E, Electrical and Electronics Engineering at, 2009-2013. B.V.B College of engineering, Hubli, Karnataka- 580031 Intermediate (+2), 2007 ... - 2020 Mar 02
Design Project
Bangalore, Karnataka, India
... Driven Verification, Assertion Based Verification • Protocols : TCP/IP EDA Tools : QuestaSim-Mentor Graphics, ISE-Xilinx Domain : FPGA front-end Design and Verification Knowledge : RTL Coding, FSM based design, Simulation, Code Coverage, Functional ... - 2020 Jan 08
... Driven Verification, Assertion Based Verification • Protocols : TCP/IP EDA Tools : QuestaSim-Mentor Graphics, ISE-Xilinx Domain : FPGA front-end Design and Verification Knowledge : RTL Coding, FSM based design, Simulation, Code Coverage, Functional ... - 2020 Jan 08
C,C++,Verilog
Bangalore, Karnataka, India
... Car Parking System with PIR Sensors (08/2019 – Present) An advanced solution to users around the world who find it difficult to manage parking problems in places such as metro stations and airports using VHDL and further implementing it on FPGA. ... - 2019 Nov 24
... Car Parking System with PIR Sensors (08/2019 – Present) An advanced solution to users around the world who find it difficult to manage parking problems in places such as metro stations and airports using VHDL and further implementing it on FPGA. ... - 2019 Nov 24