| Resume alert | Resumes 51 - 60 of 419 |
Engineering Project
Vasant Nagar, Karnataka, India
... Internship in Tenet Technetronics on “Quartus FPGA board”. It enabled me to learn about programmable logic devices such as FPGA’s and their architecture and also to use Xilinx and Quartus software to code and simulate using Verilog language. ... - 2019 Nov 13
... Internship in Tenet Technetronics on “Quartus FPGA board”. It enabled me to learn about programmable logic devices such as FPGA’s and their architecture and also to use Xilinx and Quartus software to code and simulate using Verilog language. ... - 2019 Nov 13
Verification Engineer
Bangalore, Karnataka, India
... Ltd, Bangalore From March 2016 – Currently Working Project: Verification of core sub-system for a FPGA based networking chip(SmartNIC) Understood the VirtIO DMA architecture and its interfaces, involved in the discussions of shortlisting ... - 2019 Nov 11
... Ltd, Bangalore From March 2016 – Currently Working Project: Verification of core sub-system for a FPGA based networking chip(SmartNIC) Understood the VirtIO DMA architecture and its interfaces, involved in the discussions of shortlisting ... - 2019 Nov 11
Wireless communications, digital signal processing, LTE, 4g, 5g
Bangalore, Karnataka, India
... MAJOR PROJECT (BTECH) Cordic algorithm implementation using FPGA and its application (JPEG algorithm) Implementation of simple and efficient algorithm to calculate trigonometric and hyperbolic functions which are having numerous applications in ... - 2019 Nov 06
... MAJOR PROJECT (BTECH) Cordic algorithm implementation using FPGA and its application (JPEG algorithm) Implementation of simple and efficient algorithm to calculate trigonometric and hyperbolic functions which are having numerous applications in ... - 2019 Nov 06
Engineering C
Bangalore, Karnataka, India
... Training on embedded system using AVR microcontroller Key Learning’s- Digital system Designing Hardware Interfacing of FPGA and CPLD Hobbies/Interest Reading books especially of General knowledge/ teaching Place:-Bhopal Arjun yadav Date :- - 2019 Oct 13
... Training on embedded system using AVR microcontroller Key Learning’s- Digital system Designing Hardware Interfacing of FPGA and CPLD Hobbies/Interest Reading books especially of General knowledge/ teaching Place:-Bhopal Arjun yadav Date :- - 2019 Oct 13
Developer Software
Bangalore, Karnataka, India
... Page 2 Academic Project-BE(ECE) TITLE: VITERBI DECODER DESIGN FOR SOFTWARE DEFINED RADIO ON FPGA (VLSI DOMAIN) DESCRIPTION: A) Software defined radio adapts various modulation schemes, encoding techniques by changing its configuration. SDR reduces ... - 2019 Sep 25
... Page 2 Academic Project-BE(ECE) TITLE: VITERBI DECODER DESIGN FOR SOFTWARE DEFINED RADIO ON FPGA (VLSI DOMAIN) DESCRIPTION: A) Software defined radio adapts various modulation schemes, encoding techniques by changing its configuration. SDR reduces ... - 2019 Sep 25
Design Electrical
Gottigere, Karnataka, India
... UVM Protocols : AXI, AHB, UART, I2C, SPI EDA Tools : QuestaSim – Mentor Graphics, Riviera Pro – Aldec, ISE – Xilinx Domain : ASIC/FPGA front-end Design and Verification Knowledge : RTL Coding, FSM based design, Simulation, Code Coverage, Functional ... - 2019 Sep 11
... UVM Protocols : AXI, AHB, UART, I2C, SPI EDA Tools : QuestaSim – Mentor Graphics, Riviera Pro – Aldec, ISE – Xilinx Domain : ASIC/FPGA front-end Design and Verification Knowledge : RTL Coding, FSM based design, Simulation, Code Coverage, Functional ... - 2019 Sep 11
Electronics graduate,pursuing Design for testing,verilog,digital elect
HSR Layout, Karnataka, India
... 2’s complement of a number which does the work faster than conventional method and the classical adder structure has been replaced by Ling adder for reducing delay.Therefore a faster version of multiplication algorithm can be implemented on FPGA. ... - 2019 Sep 09
... 2’s complement of a number which does the work faster than conventional method and the classical adder structure has been replaced by Ling adder for reducing delay.Therefore a faster version of multiplication algorithm can be implemented on FPGA. ... - 2019 Sep 09
Engineer Engineering
Vasant Nagar, Karnataka, India
... PROJECT UNDERTAKEN IN M.TECH : “Design and Implementation of FPGA based closed loop V/f speed control of Induction Motor Employed for Industrial Applications” Team size: 1 SEMINARS ATTENDED: PROJECT UNDERTAKEN IN B.E: “GSM Based Vehicle Battery ... - 2019 Sep 08
... PROJECT UNDERTAKEN IN M.TECH : “Design and Implementation of FPGA based closed loop V/f speed control of Induction Motor Employed for Industrial Applications” Team size: 1 SEMINARS ATTENDED: PROJECT UNDERTAKEN IN B.E: “GSM Based Vehicle Battery ... - 2019 Sep 08
Project Security
Vasant Nagar, Karnataka, India
... TeleCommunication Networking TECHNICALEXPERTISE CoreSkills:VLSIdesign Platform:Linux(redhatenterpriselinux5) Software:Cadancetool,Incisive_Enterprise_Simulator,NCSIMverilogSimulator Platform:Windows732bit Software:Xilinx12.1,FPGA:Spartan6XC6SLX45. ... - 2019 Aug 27
... TeleCommunication Networking TECHNICALEXPERTISE CoreSkills:VLSIdesign Platform:Linux(redhatenterpriselinux5) Software:Cadancetool,Incisive_Enterprise_Simulator,NCSIMverilogSimulator Platform:Windows732bit Software:Xilinx12.1,FPGA:Spartan6XC6SLX45. ... - 2019 Aug 27
Hardware Engineer
Vasant Nagar, Karnataka, India
... Cadence Virtuoso, Cadence Encounter RTL Compiler • Simulation Tool: PSpice (Spectre), OrCAD Schematic Capture, TINA Spice • FPGA Synthesis: Xilinx ISE, Vivado • Scripting: Python, Linux/Unix shell scripting, Tcl/Tk scripting • Programming Languages: ... - 2019 Aug 20
... Cadence Virtuoso, Cadence Encounter RTL Compiler • Simulation Tool: PSpice (Spectre), OrCAD Schematic Capture, TINA Spice • FPGA Synthesis: Xilinx ISE, Vivado • Scripting: Python, Linux/Unix shell scripting, Tcl/Tk scripting • Programming Languages: ... - 2019 Aug 20