Verification Engineer
Resume:
ROHIT R
Bangalore, India
*****.*********@*****.***
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Summary
Design Verification engineer with 4.5 years of experience in working with mobile/automotive/PC platforms. Looking for a challenging career in a company where I can contribute towards organization’s interests, acquire knowledge and sharpen my skills. ㅡ
Skills
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Experience
Languages : System Verilog, Verilog, SystemC, C, C++ Scripting Languages : Python, Perl
Methodologies : UVM, OVM, TLM
Tools : DVE, VCS, Virtualizer (VPA/PCT), Simics, CoMET, GTK Wave IDE/Debuggers : Visual Studio, Eclipse, Lauterbach Trace32 Intel Technology India Pvt. Ltd, Bangalore
From March 2016 – Currently Working
Project: Verification of core sub-system for a FPGA based networking chip(SmartNIC)
Understood the VirtIO DMA architecture and its interfaces, involved in the discussions of shortlisting methodologies, test plan.
Developed a memory model and test bench environment in SV/UVM to verify DMA block at subsystem level.
Currently working on developing sequences and test cases to verify the ingress and egress network traffic.
Project: Verification of NoC sub-system for 5G-RF chip (SMARTi)
Developed a test plan and updated the test bench and environment.
Wrote 30 new test cases using SV/UVM to verify the functionality of NoC sub-system and enhanced the scoreboard.
Filed bug reports, worked with RTL owner to fix the bugs and verified the fixes
Developed a python script which helps in generating the code coverage report. Project: Verification of IP blocks for 5G-RF chip (SMARTi)
Responsibilities included testing and verifying the functionality of 2 IPs in DCA block.
Enhanced the existing tests by adding randomization support.
Analyzed regression test results and fixed issues which occurred due to randomization and increased the functional coverage percentage to 90%.
Developed basic firmware tests in ‘C’.
Project: Verification of a security feature(MKTME) on server platform
Lead the development efforts for validating a new encryption feature for virtual machines running on server platform.
Ratified the requirements from stakeholders and developed a tool to validate crypto isolation among Virtual Machines on Pre-Si environment. Project: Development and verification of SystemC models for Audio sub-system
Understanding the architecture of Audio sub-system of Intel’s client platform.
Enabling DMIC capture and WoV (Wake on Voice) use cases on a virtual platform - also debugged and unblocked the long standing issue related to DMIC capture.
The above tasks were done for the first time on Pre-Si environment Infineon Technologies, Bangalore
July 2014 - June 2015 (Intern), July 2015 - Feb 2016 (SystemC Modelling Engineer) Project: Verification of Virtual Prototype for Infineon’s automotive Microcontroller
Worked on the project titled “A Fault Injection Framework using Virtual Prototyping for Embedded Software Verification” during internship period. ㅡ
Education
School of Information Science, Manipal
Post-Graduation: MSc Tech (Embedded Systems), 2015 CGPA: 9.64
Dr. Ambedkar Institute of Technology, Bangalore
Under-Graduation: BE(Electronics and Communication), 2013 79.63%
MES Vidyasagar MPL Sastry PU College, Bangalore
12th class, 2009
91.5%
The New Cambridge English School, Bangalore
10th class, 2007
93.76%
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Publications/Awards
The paper titled “A Fault Injection Framework using Virtual Prototyping for Embedded Software Verification” was published at SNUG India conference organized by Synopsys and at Infineon’s technical conference.
The poster titled “Accelerating Multi Key Encryption for Servers through Pre-silicon Enabling” was published at Pre-Silicon summit at Intel.
Secured “Division Recognition Award” for validating a security feature on server platform
Secured best Intern of the year at Infineon Technologies.
Secured 19th rank in National Level Mathematics Talent Examination. ㅡ
Declaration
I hereby declare that the information furnished above is true to the best of my knowledge
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