| Resume alert | Resumes 61 - 70 of 496 |
Design Engineering
San Jose, CA
... Simulation tools: Synopsys VCS, PrimeTime, Cadence NC-Verilog, DVE waveform viewer, Xilinx Vivado, Quartus 2, Git. Relevant concepts: SystemVerilog Assertions (SVA), Functional Coverage, Constraint Random Verification. ACADEMIC PROJECTS: Functional ... - 2020 Aug 05
... Simulation tools: Synopsys VCS, PrimeTime, Cadence NC-Verilog, DVE waveform viewer, Xilinx Vivado, Quartus 2, Git. Relevant concepts: SystemVerilog Assertions (SVA), Functional Coverage, Constraint Random Verification. ACADEMIC PROJECTS: Functional ... - 2020 Aug 05
Engineer
San Jose, CA, 95135
... History Mattson Technology, Fremont, CA 1/2018- 7/27/20 Staff Engineer in Plasma Design Group: • Designed interface boards for Wafer Etch/Strip machines using Xilinx Vivado and Cadence tools. • Performed Etch/Trip wafer machines include RF Gen ... - 2020 Aug 05
... History Mattson Technology, Fremont, CA 1/2018- 7/27/20 Staff Engineer in Plasma Design Group: • Designed interface boards for Wafer Etch/Strip machines using Xilinx Vivado and Cadence tools. • Performed Etch/Trip wafer machines include RF Gen ... - 2020 Aug 05
Engineer Electrical
San Jose, CA
... SKILLS Languages C, Python, CAPL script, Verilog, C++, microprocessor xx86 ALP Tools Vector CANalyzer, Peak, Intrepid NeoVI, TI Packet Sniffer, FMEA/HARA, Wireshark, EMI/EMC, Cadence, LabView. Lab Tool & Skills CANoe, Altium PCB, Oscilloscope, NI & ... - 2020 Jul 26
... SKILLS Languages C, Python, CAPL script, Verilog, C++, microprocessor xx86 ALP Tools Vector CANalyzer, Peak, Intrepid NeoVI, TI Packet Sniffer, FMEA/HARA, Wireshark, EMI/EMC, Cadence, LabView. Lab Tool & Skills CANoe, Altium PCB, Oscilloscope, NI & ... - 2020 Jul 26
Design Engineering
Santa Clara, CA
... TECHNICAL SKILLS Hardware Description/ Programming/Scripting Languages: VHDL, Verilog HDL, System Verilog, Raspberry Pi, Python, Perl Design Tools: Cadence (Virtuoso, Encounter), Synopsys (DC Compiler, Formality), Calibre, LabView, Xilinx ISE. ... - 2020 Jul 13
... TECHNICAL SKILLS Hardware Description/ Programming/Scripting Languages: VHDL, Verilog HDL, System Verilog, Raspberry Pi, Python, Perl Design Tools: Cadence (Virtuoso, Encounter), Synopsys (DC Compiler, Formality), Calibre, LabView, Xilinx ISE. ... - 2020 Jul 13
Electrical Engineer Design
Santa Clara, CA
... RTL Scripting, Python • Tools: Xilinx ISE, Cadence Virtuoso, Modelsim, OrCAD, PSpice, VCS, MATLAB, HSPICE, and Synopsys TCAD, Solidworks, JMP, Imatest • Other Skills: Technical writing, Business communications, Project management, Manufacturing. ... - 2020 Jul 06
... RTL Scripting, Python • Tools: Xilinx ISE, Cadence Virtuoso, Modelsim, OrCAD, PSpice, VCS, MATLAB, HSPICE, and Synopsys TCAD, Solidworks, JMP, Imatest • Other Skills: Technical writing, Business communications, Project management, Manufacturing. ... - 2020 Jul 06
Electrical Engineer Engineering
Union City, CA
... 2013 - June 2017 SKILLS C, C++, Python, MATLAB, LabView, Altium Designer, Eagle, CCS, Arduino, HSPICE, Synopsys, Cadence, Verilog, ADS, Circuits Lab Experience (oscilloscope, soldering station etc.) WORK EXPERIENCE Electrical Engineer, NASA Ames ... - 2020 Jun 27
... 2013 - June 2017 SKILLS C, C++, Python, MATLAB, LabView, Altium Designer, Eagle, CCS, Arduino, HSPICE, Synopsys, Cadence, Verilog, ADS, Circuits Lab Experience (oscilloscope, soldering station etc.) WORK EXPERIENCE Electrical Engineer, NASA Ames ... - 2020 Jun 27
Mechanical Engineer Design
San Jose, CA, 95135
... and board level guidance Provide customer with detailed concept renderings Mechanical Engineer (Contract) Cadence Design Systems – San Jose, CA November 2015 to May 2017 Developed test plans and conducted MDVT testing on new flagship product. ... - 2020 Jun 26
... and board level guidance Provide customer with detailed concept renderings Mechanical Engineer (Contract) Cadence Design Systems – San Jose, CA November 2015 to May 2017 Developed test plans and conducted MDVT testing on new flagship product. ... - 2020 Jun 26
Engineer Electrical
San Jose, CA
... Held earlier roles as Senior Member of Technical Staff at Cadence Design Systems, Senior Project Engineer at Tannon Manufacturing, and Electrical Design Engineer at Tandem Computers EDUCATION AND CERTIFICATIONS MSEE, South Dakota School of Mines and ... - 2020 Jun 22
... Held earlier roles as Senior Member of Technical Staff at Cadence Design Systems, Senior Project Engineer at Tannon Manufacturing, and Electrical Design Engineer at Tandem Computers EDUCATION AND CERTIFICATIONS MSEE, South Dakota School of Mines and ... - 2020 Jun 22
Engineer Software
Fremont, CA
... CADENCE DESIGN SYSTEMS, San Jose, CA Product Integrator Monitored daily build and release. TECHNICAL SKILLS Tools: JIRA, Confluence, Jenkins, Git, Perforce, ClearCase, Cvs, Sharepoint OS: Unix, Linux Languages: Python, Perl, Shell scripting, HTML, ... - 2020 Jun 08
... CADENCE DESIGN SYSTEMS, San Jose, CA Product Integrator Monitored daily build and release. TECHNICAL SKILLS Tools: JIRA, Confluence, Jenkins, Git, Perforce, ClearCase, Cvs, Sharepoint OS: Unix, Linux Languages: Python, Perl, Shell scripting, HTML, ... - 2020 Jun 08
Engineer Design
San Jose, CA
... *Functional debug using cadence tools, source code debug using verdi. *Hardware Description Language : Verilog. *Programming Languages : Unix,C,perl,python Experience Intel Component Design Engineer Jan 2011 - August 2015 (4 years 8 months) IP ... - 2020 May 28
... *Functional debug using cadence tools, source code debug using verdi. *Hardware Description Language : Verilog. *Programming Languages : Unix,C,perl,python Experience Intel Component Design Engineer Jan 2011 - August 2015 (4 years 8 months) IP ... - 2020 May 28