DEEPA VAIDYANATHAN

**** ******* ***** #*, *** Jose CA 95129

© 412-***-**** (addg06@r.postjobfree.com)

https://www.linkedin.com/in/deepavaidyanathan/

Summary

IP/SOC Verification engineer with 6+ years of experience in design automation and validation, within high tech environments. Execute projects on time with deeper understanding and thorough verification.Reputation of being hard working and a good team player. Specialties:

Skills:

* High level SOC specification and documentation.

*System verilog OVM/UVM testbench development and modification.

*Functional debug using cadence tools, source code debug using verdi.

*Hardware Description Language : Verilog.

*Programming Languages : Unix,C,perl,python

Experience

Intel

Component Design Engineer Jan 2011 - August 2015 (4 years 8 months) IP Validation Engineer (June 2014- Aug 2015)

* Responsible for IP validation, failure debug, customer support and release drops. SOC Validation Engineer (Aug 2012 - May 2014)

*Responsible for SOC validation for sideband interconnect of all units in multiple ASIC projects for set top box and tablet products

*Responsible for validating upstream, downstream and peer to peer connectivity validation at the PSF fabric level

*Developed directed and constrained random test-cases for multiple features in the design Design Automation Engineer (Jan 2011 to July 2012)

*Owned git-gk for key projects

*Responsible for developing scripts in perl for automation Other:

Here is a link to EDAPlayground where I have coded a testbench for gaining experience. This is a mini project to create a TB environment for APB (Advanced Peripheral Bus) protocol verification, without the DUT. Transactions are generated and can be seen in the log file

,from driver and monitor components.

https://www.edaplayground.com/x/vxR

Intel

Graduate Technical intern Jan 2010 - Dec 2010 (1 year) Responsible for regression runs, categorize failures, minor debug and generate report. Previous:

Tata Honeywell

Instrument and control engineer Nov 2003 – Aug 2004 (1 year) Invensys India Private Ltd

Systems Engineer July 1998 – Oct 2003 (5 years)

Awards and Acknowledgements

● Intel Division Recognition Award - Convergence Role modeling Award Emulation-friendly passive VIP Convergence For leading and delivery of converged TFM for emulation-friendly passive VIP enabling IP to SoC seamless reuse

● Operational Excellence Award - For excellence in Automation 2

Education

M.S - Electrical engineering; VLSI from SanJose State University (2007-2009) B.E - University of Madras; Electronics and Communication Engineering (1994 - 1998) 3

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