| Resume alert | Resumes 81 - 90 of 203 |
Electrical Engineering Assembly Line
Richardson, TX
... Tools used: Cadence, Xilinx, Design Vision, Encounter, Siliconsmart, HSPICE. Design of Portable LDO regulator (University of Texas at Dallas) November 2017 Implemented LDO circuit using 0.35um CMOS technology. Designed two stages of LDO circuit i.e. ... - 2018 Feb 26
... Tools used: Cadence, Xilinx, Design Vision, Encounter, Siliconsmart, HSPICE. Design of Portable LDO regulator (University of Texas at Dallas) November 2017 Implemented LDO circuit using 0.35um CMOS technology. Designed two stages of LDO circuit i.e. ... - 2018 Feb 26
Field Engineer Field Service
Denton, TX
... ADDITIONAL SKILLS: - Schematic Diagram Reading & Electrical Wiring - Packaging Machine Maintenance - Inventory Management - Experience with LabView, XLINX, Code Composer Studio, SPICE, PSPICE, Cadence, and MATLAB - Multiple years of experience using ... - 2018 Feb 24
... ADDITIONAL SKILLS: - Schematic Diagram Reading & Electrical Wiring - Packaging Machine Maintenance - Inventory Management - Experience with LabView, XLINX, Code Composer Studio, SPICE, PSPICE, Cadence, and MATLAB - Multiple years of experience using ... - 2018 Feb 24
Test Cases Data Entry
Allen, TX
... Environment: HP ALM Quality Center 11.5, Mortgage Cadence, ELC, Borrower Center, Desktop Originator, Windows 7, Microsoft Sharepoint, AMC Blueworks, Microsoft Office, MS Visio, UAT, End-to-End. Capital One Bank, St Cloud, MN Role: Sr. QA Analyst ... - 2018 Feb 12
... Environment: HP ALM Quality Center 11.5, Mortgage Cadence, ELC, Borrower Center, Desktop Originator, Windows 7, Microsoft Sharepoint, AMC Blueworks, Microsoft Office, MS Visio, UAT, End-to-End. Capital One Bank, St Cloud, MN Role: Sr. QA Analyst ... - 2018 Feb 12
Electrical Engineer Software
Plano, TX
... and use bench test setups, have replicated customer setups for many devices and then performed root cause analysis Used Cadence for circuit analysis and FIBs for micro-circuit edit to isolate failures and deprocess the devices to silicon layer by ... - 2018 Jan 29
... and use bench test setups, have replicated customer setups for many devices and then performed root cause analysis Used Cadence for circuit analysis and FIBs for micro-circuit edit to isolate failures and deprocess the devices to silicon layer by ... - 2018 Jan 29
Design Engineering
Richardson, TX
... EDA Tools: Design Compiler, IC Compiler II, Cadence Virtuoso, Encounter, Silicon Smart, Prime Time, Library Compiler, Tetramax, cplex, AWR Microwave Office. Miscellaneous: MATLAB, NI Multisim, NI LabVIEW, Arduino, Keil, Xilinx, Excel. PROFESSIONAL ... - 2018 Jan 28
... EDA Tools: Design Compiler, IC Compiler II, Cadence Virtuoso, Encounter, Silicon Smart, Prime Time, Library Compiler, Tetramax, cplex, AWR Microwave Office. Miscellaneous: MATLAB, NI Multisim, NI LabVIEW, Arduino, Keil, Xilinx, Excel. PROFESSIONAL ... - 2018 Jan 28
Power Electrical Engineering
Irving, TX
... Software Skills oTools: MATLAB, Simulink, Power Sim, Multisim, LTSpice, Cadence Virtuoso, PSPICE, ANSYS-MAXWELL, C, Code Composer Studio, Keil uVision5, SKM Power, PS-CAD, Lab-view, Auto-CAD, CREO, Altium and MS Office. Academic Projects Stabilizing ... - 2018 Jan 23
... Software Skills oTools: MATLAB, Simulink, Power Sim, Multisim, LTSpice, Cadence Virtuoso, PSPICE, ANSYS-MAXWELL, C, Code Composer Studio, Keil uVision5, SKM Power, PS-CAD, Lab-view, Auto-CAD, CREO, Altium and MS Office. Academic Projects Stabilizing ... - 2018 Jan 23
Electrical Engineering Design
Richardson, TX
... Spectrum Analyzer, DSO, RF Power Meter, LCR Meter, op-amp IC741 Software packages: MS Office, AWR microwave office, Cadence, FEKO, Auto cad, FPGA, Spice, P-Spice, H-spice, Kiel u vision, Verilog, HFSS, CST, ADS and Verilog Relevant Coursework: ... - 2017 Nov 18
... Spectrum Analyzer, DSO, RF Power Meter, LCR Meter, op-amp IC741 Software packages: MS Office, AWR microwave office, Cadence, FEKO, Auto cad, FPGA, Spice, P-Spice, H-spice, Kiel u vision, Verilog, HFSS, CST, ADS and Verilog Relevant Coursework: ... - 2017 Nov 18
Python Data Scientist
Frisco, TX, 75035
... GradeGPA: 3.33/4.0 Dates attended or expected graduation 2010 – 2012 Activities and Societies: Student Member of IEEE Selected IC (Integrated Circuit) Design Projects: Designed Two-stage Op-amp Based on Miller Compensation using Cadence Virtuoso. ... - 2017 Nov 17
... GradeGPA: 3.33/4.0 Dates attended or expected graduation 2010 – 2012 Activities and Societies: Student Member of IEEE Selected IC (Integrated Circuit) Design Projects: Designed Two-stage Op-amp Based on Miller Compensation using Cadence Virtuoso. ... - 2017 Nov 17
Mask design Engineering
Allen, TX
... •Expert in Cadence Virtuoso Layout editor, Mentor ICstation, ICgraph and ICED •Experience in block and top level layout; floor planning, assembly and physical verification using LVS, DRC, VPS, SPA and other required verification checks. •Proficient ... - 2017 Oct 18
... •Expert in Cadence Virtuoso Layout editor, Mentor ICstation, ICgraph and ICED •Experience in block and top level layout; floor planning, assembly and physical verification using LVS, DRC, VPS, SPA and other required verification checks. •Proficient ... - 2017 Oct 18
RPA Developer
Plano, TX
... This involves moving the CSD documents from Cadence (Vendor Portal) to USAA Content Management System (Documentum) and then mailing these documents out to members via ECT (Enterprise Correspondence Tool). This process is performed manually by a team ... - 2017 Oct 17
... This involves moving the CSD documents from Cadence (Vendor Portal) to USAA Content Management System (Documentum) and then mailing these documents out to members via ECT (Enterprise Correspondence Tool). This process is performed manually by a team ... - 2017 Oct 17