Actively Looking for Big Data Analysis with python position -Currently as Telecom Network/Software Engineer at ZTE

Core Network Engineer

Company NameZTE USA

Dates EmployedJan 2016 – Present Employment Duration1 yr 11 mos

LocationRichardson, TX

4G Cellular Network Test Engineer (Contract)

Company NameSamsung Electronics America

Dates EmployedAug 2015 – Dec 2015 Employment Duration5 mos

LocationRichardson, TX

-Verizon 4G Femtocell Network FOA Team Support.

Acceptance Test for Samsung Enterprise and Residential Femtocell.

Maintenance Window Support with VzW system engineers to complete NE upgrade and TS. Verify data and voice on femto units.

-Verizon 4G e911 Verification for Call Routing--Function and Location Verification

Working with network elements and network system content including: Femtocell, SeGW, Femto GW, MME, CSCF, NLS- Location Server, Femto Network Mgmt. System, TR069, Femto Access Point (FAP), Diameter Protocol, LCN Trace, QXDM, and Wireshark.

Software/Network Test Engineer

Company NameOrchestra Technology

Dates EmployedJun 2013 – Aug 2015 Employment Duration2 yrs 3 mos

LocationDallas, TX

-Telecom Mobile, Web FE, Server Application and DataBase Testing.

Product: End-to-End Test Intelli-Agent SW suite. ( Intelli-Agent is a network KPI monitor and performance optimization application).

Testing: Design and execute test cases ( for Feature/ Regression/ System testing), Debugging (Adb, Wireshark, QXDM, MySql ) and Troubleshooting.

-AP performance and WiFi Network Testing.

Project: Cisco Lab AP Performance Test & WiFi Problem Reporting Project--Using IA Tool to test WiFi.

-4G LTE Network Performance Testing.

Project: LTE network performance testing (Data, Voice, VoLTE, VoWiFi, AGPS etc.) and optimization for T-Mobile and other customers.

The University of Texas at Dallas

Degree NameMaster of Electrical Engineering Field Of StudyIntegrated Circuit and System GradeGPA: 3.33/4.0

Dates attended or expected graduation 2010 – 2012

Activities and Societies: Student Member of IEEE

Selected IC (Integrated Circuit) Design Projects:

Designed Two-stage Op-amp Based on Miller Compensation using Cadence Virtuoso.

Designed LDO and DCDC Converter in 0.35 um process using Cadence Virtuoso.

Designed a 16-bit ALU in IBM 0.13 um process using Modelsim, Cadence and Synopsys.

Designed and Layout a 512-bit SRAM in the IBM 90nm process using Cadence and Synopsys.

Contact this candidate