RTL to GDS II, Verilog, System Verilog, TCL, Perl, C

NIKHILA MIRIYALA

C: 816-***-**** ****************@*****.***

Summary

Seeking entry-level positon/co-op in ASIC/SoC design. Design and Verification experience with Digital IC’s Professional Experience

PG Diploma in Physical design and SoC Integration, Shastra Microsystems Jan’16 – Jun’16 Course Complete ASIC Design Flow, Floorplan, Power plan, Placement, Timing Analysis, Congestion Analysis, Clock Tree Synthesis, Routing, Physical Verification & Sing Off Analysis [IR, SI, EM, Power] with real time examples. Project “Block level design of LEON in 45nm”

Technical Lab Assistant, University of Missouri Kansas City Oct’14 – May’16 Role Assisting students with Technical tools and Software usage (Cadence, MS-Office) Solving technical problems both hardware and software Built team work skills and demonstrated strong, influential relationships with Internationals Highlights

Relevant Courses:

VLSI Design

Analog IC Design

Mixed IC Design

Verilog HDL Design

Nanoscale devices

&manufacturing

Advanced VLSI

Physical design

Computer Architecture

Digital Signal Processing

Areas of Expertise:

CMOS IC design &

fabrication fundamentals

RTL to GDS II flow

Expert in Verilog, C and

Matlab

TCL, Perl, Csh Scripting

Experience on Unix/Linux

Work under minimal

supervision

Strong problem solving skills

EDA Tools:

Simulators

NCSim Questa Synapticad

Cadence

Virtuoso Spectre Encounter

Tempus RTLCompiler

Voltus

Synopsys

Primetime ICC HSPICE

Xilinx

Xilinx ISE Vivado

Education

MSEE University of Missouri Kansas City GPA: 3.3 May’16 BSEE Jawaharlal Nehru Tech University GPA: 3.7 May’13 Projects

Crosstalk Computation at 14nm and lesser nodes Apr’16

Explored transformative new ways to do computation using crosstalk

HSPICE verification of new logics and exploited CMOS Signal Integrity Issues Physical Implementation of Leon chip in 45nm Jan’16

Delivered complete error free Physical Design flow with timing clean and optimized area

Block Description:

Macro count – 4 Clock Frequency – 250MHz IO Pins – 1500 Instance Count – 35k Metal – 9 Physical Design and verification of DTMF chip Nov’15

Met the timing across all corners in very tight schedule, power planning to reduce IR drop. Required floor planning and P&R routing, CTS, timing analysis, and fixed LVS shorts and DRC and verified the same.

Block Description:

Macro count – 4 Clock Frequency – 200 MHz Instance Count – 6k Metal – 6 IO pins – 71 Design & Verification of AMBA AXI-AHB Bridge Sep’15

Designed the bridge in Verilog and verification is done in System Verilog on Xilinx FPGA board

Achieved Large scale design comprising 236 LUT FF pairs and minimum period of 1.682ns Heavy ion Irradiation simulation of 3D NAND flash memory cell Aug’15

Designed 3D NAND Flash Cell – a SONOS cell and observed simulation results in Sentaurus TCAD Designed Standard Cell Library NAND2, NOR2, XOR2, MUX2:1, OAI3222, AOI22, D-flop in 45nm Feb’15

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