Design Engineer Electrical Engineering
Resume:
Khan A. Tarik
Austin, TX *****, USA.
Tel: 737-***-****(cell)
512-***-****(Home)
E-mail: *******@*****.***
*******@*****.***
Career Summary
Electrical Design Engineer recognized for solid knowledge of device and design flows. Seeks environment in which to analyze and solve problems while working on leading edge designs as a Frontend or Backend Design Engineer. Has particular expertise in:
Digital/RTL verification work
Block/SOC level reliability verification and mixed signal verification
Power grid design and robustness check of grid
Extensive Spice modeling for circuit analysis
Low power circuit design techniques and device modeling
Professional Experience: Intel, Senior design Engineer, Feb 2006- Present
oWorked on five different atom based SOC products and have hands on experience on FC floor planning, bump map and power grid robustness checking. Have experience in cross-site cross-team environment.
oDigital verification works: Developed UVM based test benches in system verilog for block-level functional verification in clear case Env.
oCreated and maintained detailed verification plans and reviewed them.
oGenerated and ran UPF based test cases on logic simulation models
oDebugged functional errors in the RTL model, using Verdi debug tool and based on in-depth understanding of the architecture and RTL.
oDefined and implemented functional coverage, and enhancing test bench to ensure coverage closure.
oMixed signal verification works on block level: Analyzed the analog circuit functionality to insure that both RTL and circuit designers correctly implemented the circuit specification and that the circuit complies with all required external and platform specifications using Verilog AMS model.
oUsed full featured transistor level simulation engine XA that delivers SPICE accuracy while maintaining Fast-SPICE performance and capacity. Implemented design improvement, tool and methodology refinement in RTL model and SPICE NETLIST,
oValidated design by identifying and exercising special cases for specific test, Debugged performance issues and test failures and provided robust functional fixes,
oDeveloped dedicated verification environments and tools using UNIX, while driving a complex process of exercising the design to verify its logical correctness.
oStrong discipline and attention to detail in ensuring effective and high quality validation that minimizes bug escapes and fixes.
oReliability verification works as design Engineer on FULL chip/block level: Owned the FC RV (IR EM) analysis on atom based SOC product code name Moorestown. Basically performed power and signal robustness checking.
oExecuted extensively FC static and dynamic IR drop analysis, FC EM analysis using Redhawk.
oPerformed transient analysis (ramping up or ramping down one block while the other blocks are in active mode) using Redhawk tool. Developed and Ran CPM modeling in order to estimate R die and Cdie of Chip using Redhawk tool. Ran Block level IR drop on GFX block, register files etc.
oUsed Spice Modeling for the register files for Atom based latest SOC product for generating dynamic current profile using Totem after doing lot of circuit simulations.
oReliability verification flow works on FULL chip/block level: Developed, validated the Reliability Verification flow (EM,SH and IR drop) based on drive and supported the customer across the board in Atom team and released the new version whenever it was available and finalized POR version for tool.
oResolved different issues that were related to RV tools
oESD flow Work: Performed ESD verification on atom based SOC product for verifying the FC level clamp placement and latchup condition.
oDeveloped, validated the ESD verification flow and supported the customers across the board in Atom team and released the new version whenever it was available and finalized POR version for tool.
oRFS memory/circuit design works: Designed and developed Custom Register file for atom based product. Developed the schematic, layout, ran lvs, did the formal equivalence check, performed timing analysis, ERC and rv analysis i.e. from rtl to gds file generation for RFS. Ported the bit slice schematic for RF from earlier version. Made the necessary transistor adjustments and scaling.
Intel, Component Design Engineer, Summer intern 2005
COMPUTER/SoftwareSKILLS
• Industry tools: Redhawk, Totem, Pathfinder, Virtuoso, XA, Prime time.
• Design Software: SILVACO, SCHRED, Cadence, Mentor Graphics, MAGIC, SimpleScalar, VHDL, HSpice, IRSim, OrCAD, Pspice, Matlab, MathCAD, Tecplot.
• Languages: C, System verilog, Perl, TCL/TK, LATEX.
EDUCATION
Graduate in Electrical Engineering (2005)PhD in device Physics
Department of Electrical Engineering, Arizona State University, Tempe, Arizona.
Department of Electrical Engineering, University of Southern California.
Undergrad in Electrical Engineering (1998)
Bangladesh University of Engineering & Technology (BUET), Dhaka, Bangladesh.
Journal Publications
1.K. Tarik, D. Vasileska, T. Thornton, “Quantum Mechanical Tunneling Phenomena in Metal-Semiconductor Junctions”, Superlattices & Microstructures, vol. 34,335-339(2004).
2.K. Tarik, D. Vasileska, T. Thornton, “Treatment of Interface Roughness”, Journal of vacuum science & technology. B, vol.22 (4), pp 2110-2112(2004).
3.T. Khan, S. Ahmed, D. Vasileska, T. Thornton, “Subthreshold mobility modeling of SOI MESFETs”, to be published by Kluwer in the Journal of Computational Electronics 2005.
4. K.Tarik, D. Vasileska, T. Thornton, “Sub-threshold Electron Mobility in SOI-MOSFETs and MESFETs”, IEEE Transaction of Electron Devices vol. 52, pp 1622-1627(2005).
5.K. Tarik, D. Vasileska, T. Thornton, “Effect of Interface-Roughness on SOI-MESFET Mobility and the Device Low-Power High Frequency Operation”, to appear in Journal of vacuum science & technology B.
HONORS/ACTIVITIES
DRA, SRA awards and kudos from Upper Management in Intel.
Graduate Tuition Scholarship,
oArizona State University.
oUniversity of Southern California.
Dean’s List Scholarship in BUET.
BUET Merit Scholarship.
Contact this candidate