Anushree Kasbekar

acxmhx@r.postjobfree.com acxmhx@r.postjobfree.com

****, *. ***** ****, *** #925, Austin. TX- 78746. Tel. 412-***-**** EDUCATION:

CARNEGIE MELLON UNIVERSITY Pittsburgh, PA May 2016 Master of Science in Electrical and Computer Engineering [GPA: 3.55/4] UNIVERSITY OF MUMBAI Mumbai, India. June 2013

Bachelor of Technology – Electronics: VES Institute of Technology [GPA: 3.86/4] SKILLS:

Programming Languages: Java, JSF, JSON, C/C++, Verilog, VHDL, Python Application Software: Cadence, MATLAB, Xilinx ISE, ModelSIM, AUTOCAD, EAGLE, SIMULINK, McPAT Languages: English (Fluent), Hindi (Fluent), Marathi (Native Speaker), Gujarati (Fluent). RELEVANT COURSES:

Analog Integrated Circuit Design ULSI Technology Status Advanced Digital IC Design Micro and Nano Systems Fabrication VLSI CAD: Logic to Layout System on Chip Design

Introduction to Computer Systems Signal Processing: Cognitive Video ACADEMIC PROJECTS:

1. 16-Bit Processor Design in 45nm Technology (Fall 2015)

Used Verilog to execute the 8-bit multiplication using Register file and Brent-Kung Tree Adder.

Developed a 16x16 SRAM Register file and Datapath using logical effort and circuit level Model simulations.

Designed layout and floorplan to minimize clock cycle and area.

Built the system layout from bottom to top level with clean DRC and LVS. 2. Double Tail Latch-Type Comparator Design (Fall 2015)

Designed a comparator suitable for a Flash ADC in a high speed serial link using CADENCE.

Modified design to obtain a balance between speed, offset, power and common mode voltages.

Achieved better isolation between input and output, also to operate at low supply voltage. 3. Analytical Placer (May 2015)

Built a placer for ASIC designs using a conjugate gradient analytical placement technique for a given netlist.

Used C++ to route and place a large number of gates, pins and wires in various sized polygons.

Displayed the final result obtained using Annealing and TSP. 4. Mobile Platform for 2020 (Future Tech) (Fall 2015)

Simulated a Mobile Platform using 7nm finfet based on ITRS 2013 predictions.

Used RRAM and MRAM for caches and a 21/2D Packaging.

Used McPAT to predict the Power, Performance and Area characteristics. 5. VLSI-CAD Boolean Sat Solver (March 2015)

Used C language to implement a parallel SAT Solver to find satisfying assignments for large Boolean Logic functions.Used in testing of large Digital Circuits. WORK EXPERIENCE:

ACCENTURE PVT LTD. Mumbai, India Mumbai, India

Associate Software Engineer (Developer) Nov 2013- Oct 2014

Worked in Programming Languages Java and JSF and JSON

Assessed, designed and developed an Online Interface for Scottish Police.

Co-ordinated with inter departments and interacted with on-shore teams to successfully complete phase –I of the Project. RESEARCH ASSISTANT- Carnegie Mellon Fall 2015

Efficient implementation of simulation of cell signalling networks in Verilog and C.

Simulated cell models for timely predictions of system responses to different treatments and assist clinicians in making decisions when prescribing patient-specific treatments. GLOBAL-IT Networks – Trainee 2016

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