Sourav Nandy

acubbo@r.postjobfree.com

**** ***** ***** *****, ***. 253C Austin, TX 78731 512-***-**** EDUCATION

THE UNIVERSITY OF TEXAS AT AUSTIN, M cCombs School of Business, Austin, Texas May 2016 Master of Science in Technology Commercialization

● GMAT 700, TOEFL 113

JADAVPUR UNIVERSITY, K olkata, West Bengal, India May 1 999 Bachelor of Engineering in Computer Science

● GPA 3.5

EXPERIENCE

Synopsys Inc, Noida, UP, India 2012 - 2015

R&D Engineer, Staff (2012 - present)

● Led team of 3 engineers and collaborated with 10 members across multiple teams in USA, Netherlands and China to formulate technical solutions for novel products which resulted in capturing 40% of the market share

● Architected leakage analysis engine in next generation Place and Route tool from scratch to obtain 25% overall improvement in results against a conventional flow

Magma Design Automation, N oida, UP, India 2007 - 2012 Senior Manager, Product Development (2007 - 2012)

● Collaborated with teams in USA to smoothly deliver a power flow earning $100K deal with Sandforce

● Interviewed more than 15 engineers before hiring and training 2 of them for feature development in product Talus

● Delivered technical solutions for customer chip tape outs under strict timelines to top 5 customers

● Served as single point of contact worldwide for development support related to products in low power area

● Reduced memory usage by 20X in power engine by revamping code in 3 weeks for Texas Instruments

● Created unique technology that was leveraged as a distinct offering of electromigration solutions for NEC Cadence Design Systems, N oida, UP, India 1999 - 2007 Member of Consulting Staff (2006 - 2007)

● Invented new cell selection algorithm for multi-vt optimization in product RTL Compiler that led to a patent and contributed to product market share increase from 10% to 21%

Senior Member of Technical Staff (2004 - 2006)

● Invented innovative compile time reduction technology later filed as patent and applied it to product Ambit Buildgates to get 2X benefit in compile time

● Led IP component migration after transition to India from Ireland and maintained $1M sales in revenue Member of Technical Staff (2000 - 2004)

● Provided key feature development single-handedly for product Verilog-XL and maintained revenues at $10M Software Engineer (1999 - 2000)

● First in company to port a product to 64-bit Linux platform and share best practices with 2 other teams ADDITIONAL

● Obtained 2 US Patents 200******** on Oct 4, 2011 and 200******** on Jan 26, 2010

● Published multiple papers and tutorials in internal conferences, v iz. TECCI and CTC in Cadence Design Systems

● Earned multiple ‘Excellence in Execution’ awards including one for helping raise market share of a product

● Known languages (English – Advanced, Bengali – Native, Hindi – Advanced)

● Taught Mathematics for 3 years to underprivileged children in a village school for NGO ‘Saikripa’ as part of ‘Make a Child Smile’ initiative in Cadence Design Systems

● Initiated corporate involvement in doing events for ‘Astha’, an NGO for children with physical challenges

● Work Eligibility: Eligible to work in the United States; will require visa sponsorship for full-time employment