| Resume alert | Resumes 21 - 30 of 48 |
State University Engineer
Hillsboro, OR
... Convolutional filtering, Sparse Coding, Unsupervised Feature Learning Computer Skills Languages: C/C++, Python, Perl, Matlab, Verilog, VHDL, x86 assembler Platforms: MPI, Cuda, OpenCV, Theano, Scikit-Learn, Orange Web: HTML, CSS, LAMP, AJAX, jQuery, ... - 2016 Nov 23
... Convolutional filtering, Sparse Coding, Unsupervised Feature Learning Computer Skills Languages: C/C++, Python, Perl, Matlab, Verilog, VHDL, x86 assembler Platforms: MPI, Cuda, OpenCV, Theano, Scikit-Learn, Orange Web: HTML, CSS, LAMP, AJAX, jQuery, ... - 2016 Nov 23
Electrical Engineering Engineer
Happy Valley, OR
... Skills ● Programming (C/C++/Python) ● Robotics ● Linux Ubuntu ● Matlab/LTSpice/Verilog ● Circuit Analysis/Design ● Electrical Plant Operations ● Oscilloscopes, Function Generators, and Multi-meters Education Portland State University Portland, ... - 2016 Nov 05
... Skills ● Programming (C/C++/Python) ● Robotics ● Linux Ubuntu ● Matlab/LTSpice/Verilog ● Circuit Analysis/Design ● Electrical Plant Operations ● Oscilloscopes, Function Generators, and Multi-meters Education Portland State University Portland, ... - 2016 Nov 05
Electrical Engineer Engineering
Portland, OR
... Engineering GPA: 3.5 [September 2013 - August 2016] North Seattle Community College GPA: 3.5 [September 2011- August 2013] SOFTWARE: MATLAB, Java, Python, C#, Verilog, R, LTSpice, Quartus II, Logisim, C++ (Learning), Machine Learning (Learning). ... - 2016 Nov 03
... Engineering GPA: 3.5 [September 2013 - August 2016] North Seattle Community College GPA: 3.5 [September 2011- August 2013] SOFTWARE: MATLAB, Java, Python, C#, Verilog, R, LTSpice, Quartus II, Logisim, C++ (Learning), Machine Learning (Learning). ... - 2016 Nov 03
Digital Design
Portland, OR
... Systems and Design, ASIC Modelling and Synthesis, Computer Architecture, Digital Integrated Circuit Design, System Verilog, Verilog Workshop B.E Electrical and Electronics Engineering OCT 2010-JUN 2014 o Chaitanya Bharathi Institute of ... - 2016 Oct 28
... Systems and Design, ASIC Modelling and Synthesis, Computer Architecture, Digital Integrated Circuit Design, System Verilog, Verilog Workshop B.E Electrical and Electronics Engineering OCT 2010-JUN 2014 o Chaitanya Bharathi Institute of ... - 2016 Oct 28
Design Engineer Software
Portland, OR
... Programming language: C/C++, ASM, VERILOG C/ASM tools: KEIL, CCS, Microsoft VS, chip vendor’s tools etc. FPGA Tools: Xilinx ISE, SYNPLIFY PRO, Design Complier, Mentor MODLESIM PCB tools: Cadence, Allegro, ORCAD, PROTEL, SIGRITY etc Interface ... - 2016 Oct 08
... Programming language: C/C++, ASM, VERILOG C/ASM tools: KEIL, CCS, Microsoft VS, chip vendor’s tools etc. FPGA Tools: Xilinx ISE, SYNPLIFY PRO, Design Complier, Mentor MODLESIM PCB tools: Cadence, Allegro, ORCAD, PROTEL, SIGRITY etc Interface ... - 2016 Oct 08
Test Electrical
Beaverton, OR
... Sound knowledge of verification methodology, electrical characterization, And system Verilog. Skills in installing, maintaining, and support IT equipment. Excellent diagnostic abilities on all platforms. Good understanding of various subsystem in PC ... - 2016 Sep 28
... Sound knowledge of verification methodology, electrical characterization, And system Verilog. Skills in installing, maintaining, and support IT equipment. Excellent diagnostic abilities on all platforms. Good understanding of various subsystem in PC ... - 2016 Sep 28
Design Engineering
Portland, OR
... TECHNICAL SKILLS Programming Languages –C, Python, Java Hardware Description languages – VHDL, Verilog Development/ Simulation tools- Cadence Virtuoso, ModelSim, Xilinx Vivado, Mentor Graphics Veloce Testing tools- Selenium Webdriver ACADEMIC ... - 2016 Sep 18
... TECHNICAL SKILLS Programming Languages –C, Python, Java Hardware Description languages – VHDL, Verilog Development/ Simulation tools- Cadence Virtuoso, ModelSim, Xilinx Vivado, Mentor Graphics Veloce Testing tools- Selenium Webdriver ACADEMIC ... - 2016 Sep 18
Electrical Engineer
Vancouver, WA
... * Task: Design and develop a low power solution for a Motion Estimator in video processing First was the software implementation (MATLAB), then hardware (Verilog) Software implementation: use (1) Full Search (2) Sum of Absolute Difference Algorithm. ... - 2016 Jun 09
... * Task: Design and develop a low power solution for a Motion Estimator in video processing First was the software implementation (MATLAB), then hardware (Verilog) Software implementation: use (1) Full Search (2) Sum of Absolute Difference Algorithm. ... - 2016 Jun 09
Test/ Validation Engineer
Portland, OR
... Key Skills: * Expertise: DFT, Analog & Mixed Signal Circuit, PLL, Bluetooth, RF/High-Frequency Circuit, Optical Inter-Connect * Tools: TPIE, Primetime, Debussey, Netview, Cadnav, Opus * Languages: Perl, C/C++, Assembly, RTL, System Verilog, VHDL * ... - 2015 Jul 27
... Key Skills: * Expertise: DFT, Analog & Mixed Signal Circuit, PLL, Bluetooth, RF/High-Frequency Circuit, Optical Inter-Connect * Tools: TPIE, Primetime, Debussey, Netview, Cadnav, Opus * Languages: Perl, C/C++, Assembly, RTL, System Verilog, VHDL * ... - 2015 Jul 27
Management Project
Clark County, WA
... and Networking Logic & Digital Design Xilinx Conflict Resolution LT Power Play Orcad Managing Upwards MPLAB IDE Verilog Critical Observation Dediprog VHDL Attention to Detail Impact Matlab PRESENTATIONS & CONFERENCES As intern, selected to ... - 2015 Mar 11
... and Networking Logic & Digital Design Xilinx Conflict Resolution LT Power Play Orcad Managing Upwards MPLAB IDE Verilog Critical Observation Dediprog VHDL Attention to Detail Impact Matlab PRESENTATIONS & CONFERENCES As intern, selected to ... - 2015 Mar 11