Test/ Validation Engineer

Shahriar Ferdous

Hillsboro, OR

*******.********@*****.***

Cell: 512-***-****

www.linkedin.com/in/sferdous

=== == === == = === == === == = === == === == = === == === == = === == === == = === == ===

Experienced Engineer: Test/Debug Product Development Component Debug Logic Design

Accomplished Component Debug Engineer with highly focused 4+ years of post-silicon debug experience with several ATOM (Netbook, Mobile, and Tablet Micro-Processors) System on a Chip (SoC) products.

=== == === == = === == === == = === == === == = === == === == = === == === == = === == ===

Proven success working with multiple teams and building relationships for faster project execution. Able to adapt and contribute in whatever way is needed at that time. Recognized several times at Intel for improving team output. Key Skills:

* Expertise: DFT, Analog & Mixed Signal Circuit, PLL, Bluetooth, RF/High-Frequency Circuit, Optical Inter-Connect

* Tools: TPIE, Primetime, Debussey, Netview, Cadnav, Opus

* Languages: Perl, C/C++, Assembly, RTL, System Verilog, VHDL

* Computer and Software: Cadence, Virtuoso, JMP, MATLAB, Simulink, PSpice

* Test Equipment: CMT T2000 Tester, LADA, LTM, LVX, RUBY, Oscilloscope, Logic Probe, Signal Generator,

Spectrum Analyzer, Frequency Meter

* Operating Systems: Unix, Linux, Windows

EXPERIENCE

INTEL CORPORATION

Hillsboro, OR

Product Development Engineer

5/2015-7/2015

* Contributed to design, development, and validation of the testability and manufacturability of integrated circuits from the component feasibility stage through production.

* Evaluated and developed complex test methods and software programs to convert design validation vectors and drove complex test equipment.

* Analyzed and evaluated component specification versus performance to ensure optimal match of component requirements with production equipment capability with specific emphasis on yield analysis and bin split capability.

* Inspected early customer returns with emphasis on driving test hole closure activities.

* Built Test Program modules for different IPs and validated them on CMT testers by collecting post-Si data.

* Performed Circuit Marginality Validation (CMV) by comparing post-Si data collected on CMT Testers and System platform.

INTEL CORPORATION

Austin, TX

Component Design Engineer

1/2011-5/2015

* Performed post-silicon debug on the Intel Atom SoC product line by bridging device behavior with design understanding in order to characterize and isolate yield, design, and possible customer return failures from the system bus level down to a single failing node or transistor.

* Utilized DFT, test, and physical probe tools, complemented with knowledge of computer architecture, RTL, Logic, Circuit/VLSI, process, and device physics.

* Employed verification methodologies to deterministically model DFT features in the tester environment in preparation for future products.

* Completed post-Si debug such as speed path debug, scan change debug, cache debug, and critical yield debug on testers to determine root cause of all types of silicon-based functional failures.

* Devised software tools for enhancing debug analysis capabilities for various products to increase productivity.

TEXAS A&M UNIVERSITY

College Station, TX

Department of Engineering Technology & Industrial Distribution (ETID)

Teaching Assistant (TA)

1/2009-12/2010

* Led undergraduate electronics lab and guided students to understand the basic concepts of DC and AC circuits.

EDUCATION

Texas A&M University

College Station, TX

Master of Engineering (MEng): Electrical Engineering (Analog & Mixed Signal Circuit Design)

December 2010

GPA: 3.50/4.0

Bangladesh University of Engineering & Technology (BUET)

Dhaka, Bangladesh

Bachelor of Science (BSc): Electrical & Electronic Engineering

January 2008

GPA: 3.87/4.0

Contact this candidate