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Digital Design

Portland, Oregon, United States
October 28, 2016

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Phone: 971-***-**** Email: LinkedIn: Mahesh Vara Prasad/Kumboju OBJECTIVE: Seeking Internship opportunities in the field of Digital Design, Computer Architecture and Functional Validation where I can relate my academic knowledge and gain real time work experience. EDUCATION

M.S Electrical and Computer Engineering SEP 2015-MAR 2017 o Portland State University GPA-3.7

o Coursework : System On Chip (SOC) with Programming Logic, High Performance Digital Systems, Microprocessor Systems and Design, ASIC Modelling and Synthesis, Computer Architecture, Digital Integrated Circuit Design, System Verilog, Verilog Workshop

B.E Electrical and Electronics Engineering OCT 2010-JUN 2014 o Chaitanya Bharathi Institute of Technology(Osmania University) GPA-4 o Rank 2 in the University


Programming and Hardware languages : Proficient in C,C++, Java, COBOL, SQL, Python, Verilog, System Verilog, Perl, VHDL, MATLAB

Tools: ModelSim, Xilinx, MASM, ADPART, Linux, Unix WORK EXPERIENCE

Software Program Analyst Cognizant Technology Solutions JUN 2014 – JUL 2015 o As a Software Developer on VOYA insurance projects utilizing ‘Omni script’ for the front end applications and COBOL was used to develop the backend maintenance of the projects.

o Worked on VOYA insurance - IFDS Canada projects where ‘Omni script’, a scripting language was used to refer to the details of the customers from the database. o Responsible for migrating all insurance plans onto one insurance platform, there were many platforms (SBA,EASE,VOYA), the issue was that if there are more platforms there is more code and more security required, so instead of that we have planned to migrate all the rules and regulations onto a single platform named EASE platform, so this project was named – SBA to EASE Migration Project



o Designed a Reverse Polish Notation calculator using Verilog so that the calculations could be performed faster since they don’t include the use of parentheses and few operations needed to enter to perform an operation. Tested for addition, multiplication, division, subtraction and a complex expression comprising of all these o Designed Asynchronous fully interlocked circuits using VHDL and System Verilog and verified the timing for the various signals to be asserted and de-asserted o Designed a Synchronous Counters using VHDL which is built using J-K flip-flops whose clocking inputs are connected together

o Designed a Clock divider networks using VHDL

o Designed a “three out of six word” Error detection using VHDL

Data Encryption Processor

o Simulated the application specific processor using IDEA (International Data Encryption Algorithm) in Python.

o System is designed to achieve high throughput and low latency to execute the Block Ciphers.

o Now a days data security has been a major concern, so in-order to ensure this security an IDEA algorithm has been used which is used to secure 64-bit of input data with 128- bit of a key.

o This IDEA encryption process is a symmetric encryption where the same key is used for both encryption and decryption.

o This algorithm is used for 8.5 rounds and a total of 52 sub-keys are generated from the main key.

o Scope for implementing the pipelining in the processor execution.

Multiple Elevator System Design

o Simulated and exhaustively tested the functionality of a Multi-Elevator System in System Verilog.

o System was designed to achieve low user waiting response. o System can also be expanded to any number of elevators with any number of floors. o System was also tested in an emulator and found to be synthesized. o System was designed that there were no starvation issues.

Wireless Satellite Hub

o Designed a system with a memory which has efficient way of storing the data. o Reading and writing the data to/from the system is performed by control logic with code written in Verilog.

o Used the data center which is low level memory with optimum communication cost. o Optimization of the benchmark measures: unit cost, communication cost, latency is achieved by using different size memories in efficient way.

Two-way set associative cache

o Designed a cache memory system look through cache with write-back policy. o Used the LRU replacement algorithm for the cache model. o Verilog language was extensively used for this purpose.

Vectorization of RSA Encryption Process

o Vectorized the RSA encryption algorithm using 2, 4, 8, 16 vector lanes in PYTHON. o The main aim of this project was to find out the total execution time of each of the vector lanes and draw an inference.

o It was found that with 16 vector lanes we have found that it takes less time to perform the algorithm since more parallelism was obtained. o But if more number of lanes are parallelized it was found that it takes more time to execute it was because saturation limit of the processor. o The RSA Encryption algorithm is an Asymmetric algorithm which uses two separate keys private and public keys for encryption and decryption. o Finally, awarded the one of the best project.

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