| Resume alert | Resumes 11 - 20 of 48 |
Engineer Software
Portland, OR
... Basic knowledge of VHDL and VERILOG design and implementation. Experience on real time OS (VxWorks/pSOS, Linux, Windows) and socket implementation. Experience with Quality Assurance tracking tools like HP QC, JIRA etc. Knowledge of Rational's Clear ... - 2018 Dec 04
... Basic knowledge of VHDL and VERILOG design and implementation. Experience on real time OS (VxWorks/pSOS, Linux, Windows) and socket implementation. Experience with Quality Assurance tracking tools like HP QC, JIRA etc. Knowledge of Rational's Clear ... - 2018 Dec 04
Design Engineering
Portland, OR
... Neural Networks Digital IC Design Application Specific Integrated Circuits (ASIC) Microprocessor System Design Pre Silicon Functional Verification Technical Skills • RTL Design and Verification experience using Verilog, System Verilog and VHDL. ... - 2018 Feb 12
... Neural Networks Digital IC Design Application Specific Integrated Circuits (ASIC) Microprocessor System Design Pre Silicon Functional Verification Technical Skills • RTL Design and Verification experience using Verilog, System Verilog and VHDL. ... - 2018 Feb 12
CPU Performance/Design Verification Professional Experience
Portland, OR
... (Sep’15-Jun’17) University of Pune, (Aug’11-Jun’15) TECHINCAL SKILLS Programming : SystemVerilog, SystemVerilog Assetions, Verilog, C,C++, Python, Assembly, MATLAB, Perl Tools : Synopsys DC, Design Vision, Questasim, Cadence Virtuoso, Vivado Other ... - 2017 Nov 27
... (Sep’15-Jun’17) University of Pune, (Aug’11-Jun’15) TECHINCAL SKILLS Programming : SystemVerilog, SystemVerilog Assetions, Verilog, C,C++, Python, Assembly, MATLAB, Perl Tools : Synopsys DC, Design Vision, Questasim, Cadence Virtuoso, Vivado Other ... - 2017 Nov 27
Verilog, SystemVerilog, C/C++, FPGA
Portland, OR
... Institute of Technology, University of Mumbai, India (GPA: 3.65/4.0) KEY SKILLS ● Programming: Verilog, SystemVerilog, C/C++ ● Scripting: Tcl, Perl ● EDA Suite and Tools: Xilinx Vivado, Synopsys DC & ICC WORK EXPERIENCE Project Volunteer Intern, HDL ... - 2017 Sep 23
... Institute of Technology, University of Mumbai, India (GPA: 3.65/4.0) KEY SKILLS ● Programming: Verilog, SystemVerilog, C/C++ ● Scripting: Tcl, Perl ● EDA Suite and Tools: Xilinx Vivado, Synopsys DC & ICC WORK EXPERIENCE Project Volunteer Intern, HDL ... - 2017 Sep 23
Electrical Engineer
Portland, OR
... SKILLS Language: C, C++, Java, Assembly, SQLite, Verilog, Python, Perl, Shell Scripting, OpenWRT, and Git. EDA tools: Code Composer Studio, Android Studio, Eclipse, Virtuoso, Vivado, Eclipse, Code Blocks. Expertise: RTL code, Debugging (JTAG & GDB), ... - 2017 Aug 18
... SKILLS Language: C, C++, Java, Assembly, SQLite, Verilog, Python, Perl, Shell Scripting, OpenWRT, and Git. EDA tools: Code Composer Studio, Android Studio, Eclipse, Virtuoso, Vivado, Eclipse, Code Blocks. Expertise: RTL code, Debugging (JTAG & GDB), ... - 2017 Aug 18
Design Engineer
Beaverton, OR
... Master of Science in Electrical Engineering, Expected May 2017 SRM University, Chennai, TN, India Bachelor of Technology in Electronics and Communication Engineering May 2015 TECHNICAL SKILLS Hardware Descriptive Languages: RTL Verilog, VHDL; ... - 2017 Jul 24
... Master of Science in Electrical Engineering, Expected May 2017 SRM University, Chennai, TN, India Bachelor of Technology in Electronics and Communication Engineering May 2015 TECHNICAL SKILLS Hardware Descriptive Languages: RTL Verilog, VHDL; ... - 2017 Jul 24
C, C++, HDL, circuits, algorithms, computer architecture, VLSI
Hillsboro, OR
... 970-***-**** ac0b54@r.postjobfree.com https://www.linkedin.com/in/NishitKapadia (PhD in Electrical and Computer Engineering) SKILLSET Logic design: VHDL Verilog-HDL SystemVerilog ISE (Xilinx FPGAs) Design Compiler Modelsim VIS (formal verification) ... - 2017 May 16
... 970-***-**** ac0b54@r.postjobfree.com https://www.linkedin.com/in/NishitKapadia (PhD in Electrical and Computer Engineering) SKILLSET Logic design: VHDL Verilog-HDL SystemVerilog ISE (Xilinx FPGAs) Design Compiler Modelsim VIS (formal verification) ... - 2017 May 16
Engineer Project
Beaverton, OR
VLSI Verification engineer with * years * months of professional work experience in ASIC verification using UVM & System verilog and 1 year 10 months as an Assistance Professor. Have excellent working knowledge of AHB protocol and SoC functional ... - 2017 Mar 14
VLSI Verification engineer with * years * months of professional work experience in ASIC verification using UVM & System verilog and 1 year 10 months as an Assistance Professor. Have excellent working knowledge of AHB protocol and SoC functional ... - 2017 Mar 14
Engineer Software
Sherwood, OR, 97140
... Setup and validate VTPSim (Verilog Test Pattern simulator) for chipsets products for burn in pattern validations Running burn in toggle coverage by using modelSim and VCS for chipsets products. Support our team on developing perl scripts for ... - 2017 Mar 07
... Setup and validate VTPSim (Verilog Test Pattern simulator) for chipsets products for burn in pattern validations Running burn in toggle coverage by using modelSim and VCS for chipsets products. Support our team on developing perl scripts for ... - 2017 Mar 07
Engineer Design
Portland, OR
... software using Verilog. 3.Electronic acupuncture therapy device: This product is a medical device. I worked with therapy Doctors and transformed their demands into technical requirements; I designed the firmware and software based on Cortex-M3 with ... - 2017 Jan 24
... software using Verilog. 3.Electronic acupuncture therapy device: This product is a medical device. I worked with therapy Doctors and transformed their demands into technical requirements; I designed the firmware and software based on Cortex-M3 with ... - 2017 Jan 24