| Resume alert | Resumes 61 - 70 of 2008 |
Systems Engineer Test
Oklahoma City, OK
... missile control pod and test using LabView Using the Verification Requirements, wrote Verification Test Requirements and procedures for system integration ASIC/FPGA RTL Design Engineer including micro-Architecture, Simulation, STA, and Verification. ... - 2023 Nov 26
... missile control pod and test using LabView Using the Verification Requirements, wrote Verification Test Requirements and procedures for system integration ASIC/FPGA RTL Design Engineer including micro-Architecture, Simulation, STA, and Verification. ... - 2023 Nov 26
Office Staff Secretary
West Rembo, 1215, Philippines
... EMPLOYMENT HISTORY: RTL Industries Bambang St. Sta. Cruz, Manila Office Secretary May 29, 2023 – October 28,2023 Medical Depot Ecomm Office Secretary Bambang St. Sta. Cruz, Manila Encoder/ Marketing Staff Feb.14, 2017 – March 16, 2018 Bambang ... - 2023 Nov 24
... EMPLOYMENT HISTORY: RTL Industries Bambang St. Sta. Cruz, Manila Office Secretary May 29, 2023 – October 28,2023 Medical Depot Ecomm Office Secretary Bambang St. Sta. Cruz, Manila Encoder/ Marketing Staff Feb.14, 2017 – March 16, 2018 Bambang ... - 2023 Nov 24
Signal Processing Rtl Design
Broomfield, CO
... Summary of Qualifications: ●30+ years of experience in hardware/firmware design, 25+ years of ASIC RTL design, 20+ years of being the formatter IP design team lead in the hard drive ASIC/SOC controller. ●Strong knowledge of complete ASIC design flow ... - 2023 Nov 24
... Summary of Qualifications: ●30+ years of experience in hardware/firmware design, 25+ years of ASIC RTL design, 20+ years of being the formatter IP design team lead in the hard drive ASIC/SOC controller. ●Strong knowledge of complete ASIC design flow ... - 2023 Nov 24
Senior HW FPGA Engineer
United States
... Summary of Skills and Experience: • FPGA/ASIC Digital Logic Systems Design, Implementation, Emulation, and Optimization: RTL-level architecture and detailed level design, coding, and optimization using VHDL, System/Verilog, StateCAD, schematic, etc. ... - 2023 Nov 21
... Summary of Skills and Experience: • FPGA/ASIC Digital Logic Systems Design, Implementation, Emulation, and Optimization: RTL-level architecture and detailed level design, coding, and optimization using VHDL, System/Verilog, StateCAD, schematic, etc. ... - 2023 Nov 21
Front End Solution Architect
Charlotte, NC
... Front End Engineering Backend Engineering Cloud Engineering Site Reliability Engineering Program Management Primary Tech Stack: JavaScript TypeScript React & Hooks React Native Redux & RTK NodeJS GraphQL NextJS Angular Jest & RTL <Styled-Comp> ... - 2023 Nov 20
... Front End Engineering Backend Engineering Cloud Engineering Site Reliability Engineering Program Management Primary Tech Stack: JavaScript TypeScript React & Hooks React Native Redux & RTK NodeJS GraphQL NextJS Angular Jest & RTL <Styled-Comp> ... - 2023 Nov 20
Software Engineering Electrical
Fremont, CA
... Ansible Data: ETL, Hadoop, Spark, Tableau Testing: Selenium Blockchain: Ethereum, NFT, Web3, Smart Contract Hardware: Verilog, RTL, Chip Design, Chiplet, EDA, Firmware, CUDA, UVM Leadership: Agile, SCRUM Compliance: PCI, HIPAA CERTIFICATE Azure AI, ... - 2023 Nov 18
... Ansible Data: ETL, Hadoop, Spark, Tableau Testing: Selenium Blockchain: Ethereum, NFT, Web3, Smart Contract Hardware: Verilog, RTL, Chip Design, Chiplet, EDA, Firmware, CUDA, UVM Leadership: Agile, SCRUM Compliance: PCI, HIPAA CERTIFICATE Azure AI, ... - 2023 Nov 18
Verilog, Python, C/C++
Phoenix, AZ, 85003
... Employed Synopsys Design Compiler for the synthesis of RTL (Register Transfer Level) descriptions into gate-level representations. Conducted extensive simulations and analyses using Mentor Graphics ModelSim to evaluate the performance and efficiency ... - 2023 Nov 17
... Employed Synopsys Design Compiler for the synthesis of RTL (Register Transfer Level) descriptions into gate-level representations. Conducted extensive simulations and analyses using Mentor Graphics ModelSim to evaluate the performance and efficiency ... - 2023 Nov 17
Software Engineer Senior Manager
Highlands Ranch, CO
... 2002 - April 2005 • Support assemblers (VC++, STL) for generating hexadecimal byte code from firmware RTL for DSP chips. Worked with chip designers and firmware engineers. • Designed and developed an AutoConv tool to automatically upgrade firmware ... - 2023 Nov 15
... 2002 - April 2005 • Support assemblers (VC++, STL) for generating hexadecimal byte code from firmware RTL for DSP chips. Worked with chip designers and firmware engineers. • Designed and developed an AutoConv tool to automatically upgrade firmware ... - 2023 Nov 15
Operations Manager Shift Supervisor
Nadym, Yamalo-Nenets Autonomous Okrug, Russian Federation
... Act in the capacity of Armed Responder Response Team Leader (RTL), supervision of on-site response team in the event of an elevated threat level, site contingency or Active shooter event; Liaison between site security, plant operations manager and ... - 2023 Nov 10
... Act in the capacity of Armed Responder Response Team Leader (RTL), supervision of on-site response team in the event of an elevated threat level, site contingency or Active shooter event; Liaison between site security, plant operations manager and ... - 2023 Nov 10
Entry Level Fpga Design
New Delhi, Delhi, India
... AVR MCU Area of Interest: Digital Electronics RTL Design Analog Electronics Microelectronics Advanced Vlsi design EDUCATION B.Tech, Electronics & Communication Engineering 2012 Marathwada Institute of Technology-Bulandshahr, Uttar Pradesh, India M. ... - 2023 Nov 08
... AVR MCU Area of Interest: Digital Electronics RTL Design Analog Electronics Microelectronics Advanced Vlsi design EDUCATION B.Tech, Electronics & Communication Engineering 2012 Marathwada Institute of Technology-Bulandshahr, Uttar Pradesh, India M. ... - 2023 Nov 08