Prafulla B Reddy

Phone: 303-***-****

Email: ad1fgw@r.postjobfree.com

US Citizen

LinkedIn: https://www.linkedin.com/in/prafulla-b-reddy-07905627a/

Objective:

Architect electronic solutions for ASIC and FPGA based designs

Major Professional Accomplishments:

●Architected and Implemented data path/flow design within the formatter IP of hard drive controller ASIC. Various innovations to support throughput during write and more importantly when reading from disc media were implemented. These innovations range from various modulation codes, flow through and parity check codes, and finally recently to the introduction of product codes to give RAID type capability to recover whole sectors that can be recovered when the traditional inner code associated with each sector that now resides wholly in the read channel as a LDPC codeword can’t recover the sector on its own.

●The process of actually writing/reading data to/from the hard drive media by activating signals to the drive preamp by the formatter, and when data is processed by the formatter IP has latency associated with it, due to the read channel signal processing IP block that is in between. As aerial density has grown significantly in hard drives with attendant deterioration in the bit error rate (BER), the latency mentioned above has grown especially during read signal processing, requiring significant innovation in how the formatter IP, read channel IP, and DRAM buffer manager IP in the hard drive ASIC coordinate to manage the transfer of sectors to/from the disc.

●The process of signaling to the preamp to write and read data target sectors on the media required several innovations, as the hard drive evolved from sectors having an associated header/ID on the media to being header less with all relevant information, such as tables identifying factory or field identified defective sectors in the logical sector address space and track layout parameters were stored elsewhere in the drive electronics and requiring coordinating with the servo subsystem as the hard dive is an electro-mechanical system.

●The above mentioned innovations are covered in the patent reference numbers at the end of this resume, where more details can be seen. Recipient of Seagate Tech Award, given to engineers who have contributed significantly to the success of Seagate’s Products.

Summary of Qualifications:

●30+ years of experience in hardware/firmware design, 25+ years of ASIC RTL design, 20+ years of being the formatter IP design team lead in the hard drive ASIC/SOC controller.

●Strong knowledge of complete ASIC design flow starting from RTL design to gate level.

●Familiar with industry verification methodologies such as UVM and simulation tools such as VCS.

●Started career writing firmware to validate hard drive ASIC controller, prior to ASIC controller being used by hard drive product teams in the field. Excellent skills debugging issues in the field.

●Effective communication and collaboration skills, with a proven ability to work in cross-functional teams, especially with firmware groups in the field. Member of key cross-functional team at Seagate that initiates and analyzes future technology features in drive electronics (EACT).

Education:

Bachelor of Engineering in Computer Engineering from Cal Poly Pomona (1984-1988)

Career Profile

●Seagate Technology (Longmont, CO)

●Principal Engineer 2002 to 2023

●Seagate Technology(Scotts Valley, CA)

●Senior Staff Engineer 1997 – 2002

●Staff Engineer 1992 – 1997

●Junior Engineer 1989 – 1992

●NNA Technology(Scotts Valley, CA)

●Junior Engineer 1988 – 1989

Design Experience:

●Implemented numerous design features in RTL due to previously mentioned features/innovations.

●The principal engineer in defining formatter IP interfaces with other IP blocks in the ASIC, which also needed continuous updates for the reasons mentioned above. One such interface that was essential became an industry standard interface that worked with vendor read channel IP.

●Innovated and implemented via RTL, numerous features for hard drive firmware field performance and debug improvements in the formatter IP.

●Innovated and implemented via RTL, various improvements to reduce factory test time for drives.

Design Validation and Field Test Experience:

●Worked successfully with verification engineers to validate the formatter IP.

●Formulated verification strategies to meet functional and code coverage goals.

●Lead engineer for the formatter IP team to work with hard drive product firmware engineers for formatter IP related functionality in every Seagate hard drive ASIC/SOC used the last 25 years.

●Continuously fed back lessons learnt from field experience of formatter IP usage to improve each succeeding generation design and testing methodologies.

●Devised workarounds when minor issues were found due to design bugs, so that products were never affected from having new core features implemented.

Skills:

Hardware Description Languages: System Verilog, Verilog, VHDL

EDA Tools: VCS, Synopsys DC

Hardware Platforms: ASIC, FPGA

Programming Languages: C, C++

Associated Document/Patent#: (Patent Public Search USPTO)

US-11042439-B1, US-10574270-B1, US-10382065-B1, US-10379972-B1, US-10140180-B1,

US-9935735-B2, US-9443552-B2, US-9130596-B2, US-9019640-B2, US-201********-A1,

US-8760986-B2, US-201********-A1, US-8448045-B2, US-201********-A1,

US-201********-A1, US-201********-A1, US-6295176-B1, US-5983309-A, US-5818654-A, US-5717535-A, US-5696931-A, US-5434719-A

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