Senior HW FPGA Engineer

Jose G. Betancourt Page * */**/**** *:** PM

Jose G. Betancourt 21231 Knollblossom Lane, Richmond, Texas 77407 USA ad1crv@r.postjobfree.com • Cellular Phone 954-***-**** Summary: Engineering professional offering 35+ years of experience in designing, programming, testing, provisioning, deploying, sustaining engineering, and support of electronic equipment and associated systems in an engineering environment. Highly skilled in FPGA, ASIC, CPLD and board level hardware development: planning, analysis, system design, detailed design, software/firmware integration, verification, and documentation. Possesses strong technical and methodical aptitude with an innate ability to analyze, coordinate and synthesize data independently or as part/lead of a hardware/software development team. Have excellent communications and interpersonal skills. Have extensive experience in project management as well as customer interaction at different phases of product life cycle.

Summary of Skills and Experience:

• FPGA/ASIC Digital Logic Systems Design, Implementation, Emulation, and Optimization: RTL-level architecture and detailed level design, coding, and optimization using VHDL, System/Verilog, StateCAD, schematic, etc. using toolsets such as Xilinx Vivado, Microsemi Libero and Altera Quartus. Capable of using toolset to support changes, correction, and optimization of existing third- party code. Experienced with FPGA emulation of ASIC devices.

• FPGA/ASIC Chip and Board Level Timing Analysis, Simulation and Optimization: Timing Designer, Wave Former Pro, FPGA/CPLD timing analyzer tools, etc. including writing and verifying design constraints against FPGA/ASIC synthesis and place/route implementation results. Knowledgeable in resolution of potential timing conflicts, synchronous-based design (up to 125MHz), clock domain crossings, asynchronous signal handling, etc

• Logic Synthesis, Place, Route, and Fitting: Xilinx Vivado, Microsemi Libero, Synplify Simplicity, Synopsys FPGA Compiler II/Design Compiler, Altera Quartus/QuartusPro, Xilinx ISE, Lattice ispLEVER, Altera MAX-PLUS II

• Logic Simulation, Testbenching, and Verification: Model Technology Modelsim, Source/RTL level, post-synthesis, and back- annotated timing simulation, Synopsys VCS, Viewlogic Prosim/Viewsim

• FPGA,ASIC,CPLD,and discrete Logic Families used: Xilinx:Artix7-4000-3000-CoolRunner, Altera: Cyclone5,APEX20K-Stratix- Cyclone-FLEX10K-FLEX6K-MAX3000-MAX7000-MAX8000, Microsemi-Actel:ProASIC3, IGLOO AGL60-125-250-400-Actel 1200, Atmel ATL35 0.35 um Gate Arrays, Lattice: ispXPLD-5K/ispMACH,GALs,PALs, Discrete logic: CMOS, TTL, LVCMOS, LVTTL,ECL

• Board Level, Interfacing, and Hardware System Design: 10-100-Gigabit Ethernet MAC-PHY-switch/router interfaces: MII- 25MHz/RMII-50MHz/GMII-125MHz, high-speed serial links such as LVDS, RF 2.4GHz ISM band modem/transceivers/PA/LNA, GPS timing modules: U-blox, clock generators/drivers/PLL: TI CDCEL, USART, SPI, I2C, D/A, A/D: delta-sigma etc., memory devices: SRAM/DRAM/DDR/PSRAM/Flash/EEPROM/FIFO,dual-port-RAM (Parallel,SPI/I2C interfaces), Sensors: Accelerometer- Humidity-temperature, PCI bus, VME bus, ISA/EISA PC bus, H-MVIP, UTOPIA, PLL, serial/parallel converters, state machines, memory/register mapping, iPOD interfacing, etc.

• Microcontrollers/Processors: NXP ARM7, ST Micro STM32 ARM Cortex-M4, Atmel XMEGA128, Atmel SAM9G ARM9, Motorola PowerQuicc (II) MPC360/MPC860/MPC8255/MPC8260, Intel 80x86, Motorola 680x0, Atmel ATMEGA32/64/128, ARM7.

• Board level Design and Schematic Capture: Experienced in communicating and reviewing high speed requirements with PCB layout engineers, Altium Schematic and PCB Viewer, Mentor/Veribest, Zuken Redac Cadstar, OrCAD, Protel Advanced Schematic, Viewlogic ProCapture/Viewdraw, Cadence Concept/Composer, IBIS signal integrity modeling.

• Integration, failure analysis, and testing at chip, board, and system levels: digital and analog oscilloscopes, logic analyzers, signal generators, processor/FPGA/CPLD emulator/debug probes, etc.

• Communications and Networking Systems: FTTP GPON and BPON OLT/ONT, Digital Loop Carrier, TDM, POTS and T-carrier bearer/signaling (T1/E1), ATM AAL-1/5, SONET, CCSDS Space Data System-based Spacecraft data capture/processing, serial/parallel interfaces, frame synchronization, error coding/decoding, TCP/IP, etc.

• Software and Firmware design and coding: C, Ada83, Forth, 80x86/680x0 Assembler

• Operating Systems used: Windows, Linux, Solaris, VxWorks RTOS, Exceed X-Client/Server

• Office PC Applications: Microsoft Project, Visio, Word, Excel, Powerpoint, Codewright, Notepad++,etc. Most Recent Work Experience:

Velentium, Katy, Texas July 2021 to present

Electrical and Embedded Systems Hardware Engineer

• Development and documentation of FPGA designs for application in medical devices. Using Lattice iCE40 and Microsemi SmartFusion2 FPGAs using vendor tools and Verilog to support data capture and stimulus generation in medical devices. Oceaneering International, Inc, Jacobs JETS Contract, Houston, Texas January 2020 to July 2021 Electronics Design Engineer

• Assigned as lead engineer for the development of a Microsemi ProASIC3 A3PE3000 FPGA for the Main Electronics Package

(MEP) subsystem of the Plasma Diagnostic Package (PDP) for NASA’s Power and Propulsion Element (PPE) of the Lunar Gateway project.

o MEP performs PDP Sensor Biasing (D/A components), Data Collection (A/D and SRAM components), & Spacecraft Communications under the control of the FPGA. Jose G. Betancourt Page 2 6/12/2022 4:30 PM

o The PDP will enable collection of plasma plume data in orbit from the PPE ion propulsion system. o The PDP consists of a Main Electronics Package (MEP), discharge current sensors and probes housed in a Thruster Probe Assembly (TPA).

o The PDP will enable collection of plasma plume data in orbit from the PPE ion propulsion system.

• Completed preliminary design, implementation, test benching, and prototype testing using VHDL components, including a vendor- licensed PCI core IP, under the Microsemi Libero FPGA development package.

• Currently implementing engineering design unit version of the FPGA.

• Participate in the design and implementation of other MEP elements such as the Power Sensor and Control Board (PSCB) as well as internal cabling and other components using Altium schematic and PCB design entry tools. L3 Harris TECHNOLOGIES, Palm Bay, Florida August 2019 to January 2020 Lead, Electrical Engineer 5

• Assigned as lead engineer for the development of Ultrascale FPGA Integrated Core Processor (ICP) subsystem in a military avionics’ application.

• Completed preliminary design of subsyetem using VHDL components within the company’s development environment. Lockheed Martin Corporation, Owego, New York April 2019 to August 2019 Firmware Engineer Sr Staff

• Assigned as lead engineer for the development of Cycle 5 FPGAs controller boards for military avionics applications. Completed preliminary design using System Verilog component using the company’s advanced development environment including QuartusPro and Jenkins-based regression test server and System Verilog.

• Completed timing analysis and constraint entry for three Cyclone 5 based existing FPGA designs. Completion resolved issues found in integrating the FPGA designs into the system hardware. Wireless Seismic Inc, Sugar Land, Texas November 2017 to January 2019 Senior Digital Hardware Engineer

• Participate in all phases of system development and implementation: system and board level design, PCB layout, engineering test and validation, documentation, and release to production.

• As part of the RT System 3 development team:

o participated in the detailed design and implementation of a dual-board-single-geophone-channel DART. DART uses single board based on an ARM Cortex-M4 CPU. DART communicates via the enhanced three band RF modem built into the radio board. DART dual board also implements the analog channel based on a 32-bit delta-sigma A/D. o participated in the detailed design and implementation of a single-board-single-geophone-channel Mote:

Mote uses single board based on an ARM Cortex-M4 CPU, communicates via the enhanced three band RF modem built into the single board and implements the analog channel based on a 32-bit delta-sigma A/D. o participated in the detailed design and implementation of a single-board GRU:

single board based on an ARM Cortex-M4 CPU which communicates via the enhanced three band RF modem built into the single board.

• Develop and monitor electronic and electrical component compliance to system requirements and customer ever-changing needs.

• Analyze and resolve issues resulting out of customer operation of existing deployed systems

• As part of the RT System 2 development and support team: o participate in sustaining engineering of three-geophone-channel Source Interface Unit (SIU). SIU uses a single board based with dual ST Micro STM32 ARM Cortex-M4 processor: one for timing, control, and Ethernet interface/switch functions; a second one for analog A/D acquisition, formatting, and oversample filtering. SIU single board implements the timing functions using a timing block implemented in an AGL125 FPGA (VHDL). It also implements the four analog channels based on 32-bit delta-sigma A/Ds as well as an AGL250 FPGA (VHDL) implementing data acquisition, test signal generation, commanding, and control functions. Design and implement any needed changes to these two FPGA (VHDL)s based on the three-channel WRU FPGA (VHDL) design plus the new timing block with additional enhancements for interfacing with external source control and trigger inputs. Each FPGA (VHDL) also includes a microprocessor interface. Timing clock discipline of the SIU is managed by the FPGA (VHDL)’s timing block via the unit’s GPS module.

o participate in sustaining engineering of single-board-single-geophone-channel WRU. WRU uses single board based on a ST Micro STM32 ARM Cortex-M4. WRU communicates via the enhanced 5Mbps RF modem built into the single board. WRU single board also implements the analog channel based on a 32-bit delta-sigma A/D as well as an AGL125 FPGA (VHDL) implementing data acquisition, test signal generation, commanding, and control functions as well as a special-purpose timing block. Designed and implement needed changes to the FPGA (VHDL) based on the three-channel WRU FPGA (VHDL) design plus the timing block. It also includes the microprocessor interface intended to allow for direct firmware command and control of channel functions as well as parallel reading of the internal sample data FIFO. Timing clock discipline of each system unit is managed by the FPGA (VHDL)’s timing block from the unit’s GPS module or from the radio link from an uplink unit. 1st Detect, Webster, Texas April 2016 to November 2017 Electrical Digital Engineer V

Jose G. Betancourt Page 3 6/12/2022 4:30 PM

• Assigned to support documentation, changes, corrections, and optimization of existing third-party code for an Artix7 XC7A200 FPGA (VHDL) used as the heart of the controller board for a portable mass spectrometer instrument as well as design code and test the implementation of additional components.

o Completed re-architecting and re-implementing the PWM control algorithm for the system’s cooling fan making use of the FPGA (VHDL)’s temperature sensor and XADC component. o Completed re-architecting and re-implementing additional enhancements to the data flow of the control FPGA

(VHDL).

• Planned and executed the signal integrity verification test plan for the mass spectrometer control board.

• Involved in preliminary system requirements analysis and preliminary design for next generation spectrometer control system slated to be based and implemented using next generation FPGA (VHDL) technologies such as Xilinx Zynq. Wireless Seismic Inc, Sugar Land, Texas July 2010 to April 2016 Senior Digital Hardware Engineer

• Initially assigned to board level re-design and feature enhancement for the RT 1000 scalable, real-time, cable-free (wireless telemetry and data) seismic data acquisition system. System consisted of low-power Base Station Unit (BSU) and single geophone channel Wireless Remote Unit (WRU). Both units use main board based on dual processors: Atmel XMEGA128 (timing and control) and Atmel SAM9G ARM9 (analog A/D acquisition, formatting and oversample filtering or Ethernet interface). Both units communicate via 1Mbps RF modem daughter card operating in the 2.4GHz ISM band using company-proprietary protocol. WRU used single analog channel daughter card based on a 32-bit delta-sigma A/D as well as an AGL60 FPGA (VHDL) implementing data acquisition, test signal generation, commanding, and control functions accessed by the ARM9 processor via SPI interface. Timing clock discipline of each system unit managed by XMEGA processor from the unit’s GPS module or from the radio link from an uplink unit (WRU).

• As part of the next-generation RT System 2 development: o assigned to design and implement an enhanced 5Mbps RF modem daughter card. o participated in the detailed design and implementation of the Line Interface Unit (LIU) and in the re-design and implementation of the single geophone channel WRU. Both system units use main board based on dual processors: Atmel XMEGA128 (timing and control) and Atmel SAM9G ARM9 (analog A/D acquisition, formatting and oversample filtering or Ethernet interface/switch). Both units communicate via the enhanced 5Mbps RF modem daughter card. WRU uses the same single analog channel daughter card used in RT 1000 system. Timing clock discipline of each system unit managed by XMEGA processor from the unit’s GPS module or from the radio link from an uplink unit

(WRU). Designed and implemented LIU SPI multiplexing and routing AGL60 FPGA (VHDL). o participated in the detailed design and implementation of a three-geophone-channel WRU. WRU uses main board based on dual processors: Atmel XMEGA128 (timing and control) and Atmel SAM9G ARM9 (analog A/D acquisition, formatting, and oversample filtering). WRU communicates via the enhanced 5Mbps RF modem daughter card to the main board. WRU uses an enhanced analog channel secondary card based on ST Micro STM32 ARM Cortex-M4 processor, 32-bit delta-sigma A/D as well as an AGL250 FPGA (VHDL) implementing data acquisition, test signal generation, commanding, and control functions for all three channels. Designed and implemented the multi-channel FPGA (VHDL) based on original single-channel design with many additional enhancements, including a microprocessor interface intended to allow for more direct firmware command and control of channel functions as well as parallel reading (vs original SPI) of the internal sample data FIFO for each channel. Timing clock discipline of each system unit managed by XMEGA processor from the unit’s GPS module or from the radio link from an uplink unit. o participated in the detailed design and implementation of a single-board-single-geophone-channel WRU. WRU uses single board based on a ST Micro STM32 ARM Cortex-M4. WRU communicates via the enhanced 5Mbps RF modem built into the single board. WRU single board also implements the analog channel based on a 32-bit delta- sigma A/D as well as an AGL125 FPGA (VHDL) implementing data acquisition, test signal generation, commanding, and control functions as well as a special-purpose timing block. Designed and implemented the new FPGA (VHDL) based on the three-channel WRU FPGA (VHDL) design plus the new timing block. It also includes the microprocessor interface intended to allow for direct firmware command and control of channel functions as well as parallel reading of the internal sample data FIFO. Timing clock discipline of each system unit is managed by the FPGA (VHDL)’s timing block from the unit’s GPS module or from the radio link from an uplink unit. o participated in the detailed design and implementation of a three-geophone-channel Source Interface Unit (SIU). SIU uses a single board based with dual ST Micro STM32 ARM Cortex-M4 processor: one for timing, control, and Ethernet interface/switch functions; a second one for analog A/D acquisition, formatting, and oversample filtering. SIU single board implements the timing functions using a timing block implemented in an AGL125 FPGA (VHDL). It also implements the four analog channels based on 32-bit delta-sigma A/Ds as well as an AGL250 FPGA (VHDL) implementing data acquisition, test signal generation, commanding, and control functions. Designed and implemented these two new FPGA (VHDL)s based on the three-channel WRU FPGA (VHDL) design plus the new timing block with additional enhancements for interfacing with external source control and trigger inputs. Each FPGA

(VHDL) also includes a microprocessor interface. Timing clock discipline of the SIU is managed by the FPGA

(VHDL)’s timing block via the unit’s GPS module.

o participated in the detailed design and implementation of a single-board-three-geophone-channel WRU. WRU uses single board based on a ST Micro STM32 ARM Cortex-M4. WRU communicates via the enhanced 5Mbps RF modem built into the single board. WRU single board also implements the three analog channels based on 32-bit delta-sigma A/Ds as well as an AGL250 FPGA (VHDL) implementing data acquisition, test signal generation, commanding, and control functions as well as the special-purpose timing block. Designed and implemented the new FPGA (VHDL) based on the three-channel WRU FPGA (VHDL) design plus the timing block from the single-channel Jose G. Betancourt Page 4 6/12/2022 4:30 PM

WRU FPGA (VHDL). It also includes the microprocessor interface intended to allow for direct firmware command and control of channel functions as well as parallel reading of the internal sample data FIFOs. Timing clock discipline of each system unit is managed by the FPGA (VHDL)’s timing block from the unit’s GPS module or from the radio link from an uplink unit.

• Also was assigned concurrently to lead and complete the process for FCC and CE compliance certification of the RT System 2 LIU and WRU units. Certification was completed successfully. o Responsibility for new FCC and CE compliance certification of the RT System 2 units has been successfully turned over to full-time certification engineer. Continued to act as back up resource for certification activities.

• Participate in all phases of system development and implementation: system and board level design, PCB layout, engineering test and validation, documentation, and release to production.

• Develop and monitor electronic and electrical component compliance to system requirements and customer ever-changing needs.

• Analyze and resolve issues resulting out of customer operation of existing deployed systems. Jacobs Technology, ESCG/ NASA JSC, Houston, Texas June 2008 to July 2010 Sub-system Manager

• Assigned as Sub-system Manager for the Space-to-Space Communications System (SSCS) and Trajectory Control Sensor (TCS) sub-systems at NASA’s Johnson Space Center.

o The SSCS is an Ultra High Frequency (UHF) Time Division Multiple Access (TDMA) sub-system that provides multiple space vehicles containing portions of the SSCS the capability to transmit and receive voice and data. The SSCS allows vehicles that are in close proximity to transmit and receive voice, commands, and telemetry directly via radio frequency (RF) links.

o The TCS is a combined pulse and CW scanning laser ranger sub-system designed for use as a Shuttle/Orbiter tool providing relative range, range rate, bearing and bearing rate data to a passively cooperative target, in the form of an optical retro reflector (retro).

• Generate and maintain sub-system project action item list and weekly reports to project management.

• Technical leadership of all aspects of subsystem hardware usage, including detailed knowledge of hardware design, test, operational procedures, performance requirements and characteristics, hardware inventory and deployment, and anomaly history.

• Leadership of the subsystem problem resolution team (PRT).

• Technical liaison and single point of contact with the responsible NASA Space Shuttle and Space Station Project Office, Mission Operations Directorate, and Engineering Directorate; including monthly technical status, configuration change board (CCB) presentations, and technical representation at applicable project level and mission operations boards.

• Evaluation of change requests (CR) and proposed system upgrades. Generation and update of Government Certification Acceptance Requests (GCAR).

• Coordination of mission support activities. On-call mission support.

• Coordination of hardware testing, processing, and logistics in support of flight deliveries, repair, replacement, and other activities.

• Support of crew bench reviews and debriefings, test readiness reviews (TRRs), and launch site testing.

• Technical signature authority for certification of flight readiness, Failure Investigation Action Report (FIAR) closures, Discrepancy Report (DR) dispositions, Task Performance Sheet (TPS) execution, waiver and exception requests, configuration Change Requests (CRs), revision change notices (RCNs), launch site and mission action requests (Chits), generation and revision of test procedures, operations manuals, and technical specifications. Education

• Johns Hopkins University, Laurel, Maryland 1994

M.S., Computer Science, GPA: 3.3

• Johns Hopkins University, Laurel, Maryland 1988

M.S., Electrical Engineering, GPA: 3.2

• Capitol College, Laurel, Maryland 1981

B.S., Electronic Engineering Technology, GPA: 3.55

• Montgomery College, Rockville, Maryland 1979

A.A., Electronic Engineering Technology, GPA: 3.3

Training, Conferences, and Seminars

Xilinx Embedded Systems Design with Vivado Faster Technology/Xilinx, Richmond, Texas 2017 IGLOO2 Design Flow Seminar Microsemi/Avnet, Sugar Land, Texas 2014 SmartFusion2 Design Flow Seminar Microsemi/Avnet, Sugar Land, Texas 2013 Electromagnetic Compatibility Seminar Henry Ott Consultants, Sugar Land, Texas 2013 Verilog for FPGA/ASIC, Doulos, Miramar, Florida, 1999 VHDL for FPGA/ASIC, Doulos, Sunrise, Florida, 1998 FPGA/CPLD Synthesis with VHDL, Synopsys, 1998

High-Speed Digital Design, Howard Johnson, Sunrise, Florida, 1998 High-Speed Design Flow Methodology, Cadence, Sunrise, Florida, 1998 Jose G. Betancourt Page 5 6/12/2022 4:30 PM

Personal

Married. US Citizen. No travel restrictions. Will consider relocation. Bilingual: Native verbal and written fluency in Spanish. Have had beginner exposure to German language.

References and Salary History available upon request. Publications

• “High Performance CCSDS Processing Systems for EOS-AM Spacecraft Integration and Test.” Proceedings of the 1995 International Telemetering Conference. Las Vegas, Nevada, November 1995. Describes ASIC-based CCSDS return-link data capture and processing systems developed to support testing and verification of the NASA/ESA EOS- AM spacecraft. Functions performed by these systems include frame synchronization, Reed Solomon forward error correction, fill frame removal, virtual channel processing and sorting, and packet telemetry service processing.

• “Dynamic Adaptive Phase Alignment Circuit .” Patent Application, February 2005. Interface Circuit for a FTTH BPON Media Access Controller and an Optical Line Termination Transceiver Module

• “Method to Make an ONT Behave as a Rogue ONT.” Patent Application, March 2005. Analog and Digital Circuitry to cause a FTTH BPON Optical Network Terminal (ONT) to affect transmissions from other ONTs on BPON network. Affiliations

• Institute of Electrical and Electronic Engineers (IEEE), 1982 to present

• IEEE Communications Society, 1982 to present

Additional Work Experience

Ion Marine Imaging Systems, Stafford, Texas March 2007 to June 2008 Staff Electrical Engineer

• Assigned as Electrical Systems Engineer on VSO retrievable ocean bottom seismic imaging system.

• Participate in all phases of system development and enhancement for improved operation.

• Oversee diagnostic feature enhancements for measuring array leakage and communication link signal strength monitoring.

• Develop and monitor electronic and electrical component compliance to system requirements and customer ever-changing needs.

• Monitor and review development of electrical sensor and other system components by outside contractor(s).

• Write and oversee performance of system and component acceptance test pans and procedures.

• Analyze and resolve issues resulting out of customer operation of existing deployed systems.

• Technologies used include: Freescale 9S12 processors, Xilinx FPGA (VHDL)s, RS485 and LVDS serial communications links, current mode power supplies, Sigma-Delta A/D converters and DSP filter/processor system components, etc. Niles Audio Corporation, Miami, Florida August 2005 to March 2007 Principal Design Engineer

• Currently in initial stages of hardware development for company’s new line of LCD-based remote controllers for home entertainment and multizone audio system application.

• Lead hardware design engineer for development of company’s industry-award winning flagship ICS multi-zone multi-zone whole- building/house audio system ICS.

• Design, re-design, integrate, and test at component, board, and system level using Orcad schematic capture, and AHDL/Verilog HDL. Communicate and review board layout requirements with PCB layout engineers.

• Designed, implemented, and tested four additional system source and control boards in the past five months.

• Technologies used include Ethernet NIC (Davicom DM9000) and switches, Altera CPLDs, Atmel ATMEGA 32/64/128 microcontrollers, Sharp ARM7 processors, IR signal switching logic, HD-Radio modules, DAB Radio modules, iPOD interfaces, SPI and I2C interfaces, touch-sensitive LCD display screens, NiMH battery charger, analog audio amplifiers, iPOD audio/video/control interfaces, etc.

Tellabs, Inc (formerly Advanced Fibre Communications), Miramar, Florida 1998 to July 2005 Lead Engineer (formerly Sr. Engineer)

• Developing PLOAM processing component of prototype FTTH Gigabit Passive Optical Network (GPON) Media Access Controller chip (to be prototyped as FPGA (Verilog) for eventual implementation as an ASIC). The GPON MAC ASIC will implement the TC and MAC layer functions of the G.984 GPON specification.

• Provide company-wide system debug, board-level hardware and software application support for TDM serial backplane timeslot interchange ASIC which is a critical component of the company’s AccessMax platform. Regarded as “expert” in timing and controller switchover features of the system and ASIC.

• FPGA emulation of Atmel ATL35 0.35 um Gate Arrays ASIC implementation allowing test of logic prior to ommitment to final silicon implementation.

Jose G. Betancourt Page 6 6/12/2022 4:30 PM

• Designed, simulated, and tested FTTH BPON OLT MAC to optical transceiver 150MHz+ serial data interface circuit using Lattice ispXPLD-5K CPLD. Re-designed CPLD to adapt operation for new MAC ASIC implementation.

• Designed, simulated, and tested FTTH BPON ONT Sleep Mode power-control and serial interface circuit using Xilinx CoolRunner CPLD. Re-designed CPLD to add Rogue ONT emulation and testing features.

• Formed part of FTTH OLT and ONT BPON system prototype development team that traced system-critical functional error to its root cause: bug in vendor-provided processor microcode implementation of AAL1 protocol. Provided ideas for non-service-affecting work-around as well as final resolution prior to system demo to major customer.

• Designed, simulated, and tested FTTH BPON OLT 256-channel bearer and signalling mapping interface FPGA (Verilog). It connected the AccessMax platform TDM serial backplane timeslot interchange ASIC to the PMC Sierra AAL1Gator ASIC via an H- MVIP interface. FPGA (Verilog) was implemented using an Altera EP20KE100 device.

• Designed, simulated, and tested Voice-over-Packet 672-channel bearer and signalling mapping interface FPGA (Verilog). It connected the AccessMax platform TDM serial backplane timeslot interchange ASIC to the Entropia AAL1 Voice-over-Packet DSP ASIC via an H-MVIP interface. FPGA (Verilog) was implemented using an Altera EP20KE200 device.

• Re-designed bearer and signaling mapping FPGA (Verilog)s to add single-channel data capture and test features.

• Designed, simulated, and tested CPU controller timing subsystem and microprocessor interface components of the Wide Band Gate Array (WBGA). This ASIC is used by boards connected to the AccessMax platform to interface with the system’s TDM serial backplane. It also provides the system’s overall clocking and timing reference synthesis as well as controller and reference switchover mechanism. ASIC was implemented using the Atmel ATL35 0.35 um Gate Array process. As part of ASIC development team, participated in overall ASIC synthesis, timing analysis, scan test path insertion, layout, back-annotated simulation, test plan development and execution, data sheet documentation, and final release to manufacturing.

• Designed, and tested MPC860-based processor card used in the RSC24 and UMC1000 Digital Loop Carrier equipment. Led development from requirements to final testing.

• Re-designed existing 68HC16 based processor card used in the RSC24 Digital Loop carrier equipment in order to accommodate larger Flash memory. Re-design involved re-map of entire processor memory and peripheral devices.

• Developed an Altera 6016 FPGA (Verilog) for the International Data Link processor board of the UMC1000 Digital Loop Carrier to process HDLC data between the custom backplane interface ASIC and the MPC860 and MUSYCC HDLC control devices.

• Developed an Altera 7032 CPLD for the International Data Link processor board of the UMC1000 Digital Loop Carrier to provide PCI bus arbitration amongst the built

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