Adarsh Ravindra Anvekar

Tempe, Arizona ad08ty@r.postjobfree.com 480-***-**** LinkedIn

SUMMARY

I am a graduate student at Arizona State University seeking job opportunities in Chip design, verification and validation. EDUCATION

ARIZONA STATE UNIVERSITY Tempe, Arizona Aug 2022 - May 2024 Master of Science, Computer Engineering (Electrical Engineering) GPA 3.6/4 Coursework- Digital System and Circuits, VLSI Design, Advanced Silicon Processing, Computer Architecture II, Foundation of Algorithms, Introduction to Electric and Autonomous Vehicles, Python for Rapid Engineering Solutions. Visvesvaraya Technological University Belgaum, India Aug 2017 – Aug 2021 Bachelor of Engineering, Electronics and Communication Engineering GPA 3.8/4 Coursework- VLSI Design, Digital Electronics, Analog Electronics, Verilog and VHDL, Microprocessors. TECHNICAL SKILLS

Programming Languages: Verilog, System Verilog, UVM (Universal Verification Methodology), VHDL, C/C++, Python, MATLAB.

EDA Tools: Cadence Virtuoso, HSPICE, ModelSim, Intel Quartus, Synopsys Design Compiler, RedHawk.

Operating Systems: Linux, ARM, Keil uVision, Arduino, Ubuntu. PROFESSIONAL EXPERIENCE

Electrical Engineering Intern CISCO India Aug 2020 – Sep 2020

Collaborated with the engineering team and self-motivated to implement various clock gating techniques using industry-standard tools.

Employed Synopsys Design Compiler for the synthesis of RTL (Register Transfer Level) descriptions into gate-level representations. Conducted extensive simulations and analyses using Mentor Graphics ModelSim to evaluate the performance and efficiency of the clock gating techniques.

Developed a novel, optimized clock gating technique by comparing the simulation results obtained with different approaches. This innovative approach effectively addressed critical issues such as glitches and hazards within the design.

Achieved a remarkable 70% reduction in power usage by successfully implementing RTL clock gating, reducing the dynamic current consumption of a 200K-gate ASIC from 280 mA to 84 mA. System Engineer Tata Consultancy Services India July 2021 – July 2022 Performed detailed transaction analysis for American Express Card Members, identifying and validating issues. Utilized Python and SQL to resolve problems, clean applications, and eliminate bugs. Applied strong problem-solving skills to enhance system performance. Effectively communicated with clients and collaborated with team members. Proficient in tools such as CAS HOD, ServiceNow, nG1 CAS, and Radar Portal. PROJECTS

ASIC Acceleration for Graph Convolutional Neural Networks (RTL2GDSII Flow) Fall 2023

Developed Verilog code for the Graph Convolutional Neural Network (GCN) module and thoroughly tested its functionality. Utilized Design Compiler to synthesize the Verilog design, resulting in the generation of a netlist that was verified for correctness.

Employed Innovus for automated place-and-route (APR) tasks, optimizing the physical layout and measuring power consumption. Exported the GDS layout file, which serves as the physical representation of the ASIC design. Integrated the GDS layout into Virtuoso layout tool for further refinement and verification. The total area of the ASIC design was measured at 106.78 mm^2, highlighting the efficient use of physical space. Branch Prediction and Cache Replacement Techniques on GEM 5 Fall 2023

Successfully implemented and modified components of the GEM5 (Gem5-Education and M5 Simulator) simulator using C++ to study branch prediction and cache replacement mechanisms.

Designed and implemented a GSELECT, an advanced branch prediction mechanism, within a microarchitectural context.

Implemented IPV (Index, Position, and Validity) based LRU cache replacement policy which showed better HIT rate than basic LRU policy. Custom Design and Characterization of a D Flip-Flop and Adder using ASAP 7nm PDK Spring 2023

Designed transistor level schematic for a D Flip-Flop and an Adder. Performed pre-layout simulations to verify the functionality of both the cells and simulated transient behavior to ensure proper operation under different load values.

Created a physical layout of these cells based on their schematic design and ensured that their layout meets the minimum size, spacing, and electrical constraints specified by the PDK. Conducted post-layout simulations to evaluate the performance of the cells, considering parasitic effects.

Determined the clock-to-Q delay of the cells as well as the setup times for rising and falling transitions. Design of Integrate and Fire Neuron using SAED 32nm PDK Fall 2022

The IF Neuron was implemented using the D flip-flop and adder, it consists of four input neurons (x0-x3) and four synapses (wo-w3) with a total area of 111.59 um^2. Performed various simulations on the schematic to verify that the circuit meets our specifications and behaves as expected.

Created a layout for the designed circuit based on the foundry's design rules and the 32nm PDK. Used Synopsys IC Validator to perform DRC and LVS tests, as well as clocked the speed at 2 GHz. Also, simulated the post-layout design to account for parasitic and ensured that the circuit meets its specifications in the final layout. Performed timing analysis to ensure that the IF neuron operates within the desired time constraints. CERTIFICATIONS

1. UVM for Verification by Udemy, May 23rd, 2023.

2. Verilog HDL Fundamentals for Digital Design and Verification by Udemy, April 5th, 2023. 3. Computer Architecture by Princeton University via Coursera, July 24th, 2023. 4. Programming, Data Structures and Algorithms Using Python by NPTEL, Sep 29th, 2019. ACHIEVEMENTS

Arizona State University: Graduate Service Assistant Jan 2023-May 2023 o Teaching Assistant and Grader for Hardware Design Languages and Programmable Logic (EEE 333)

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