YOGESH KUMAR

M. Tech -VLSI DESIGN-****

Centre for Development of Advanced Computing(C-DAC)

C-56/1, Block C, Institution Area, Sector-62, Noida,

Uttar Pradesh 201307,UP

CONTACT DETAILS

***/*,*,**jay Park Maujpur Delhi

Mob: +91-975*******, 989*******

-ad0xvk@r.postjobfree.com

-ad0xvk@r.postjobfree.com

PROFILE

To obtain an entry-level position in an organization that will encourage me to utilize and enhance my skill sets in the field of Verification IP’s, development of Memory and Interconnect protocols with ASIC/FPGA design while gaining valuable work experience in a team oriented environment.

AREAS OF EXPERTISE

Software Proficiency:

EDA Tools : ModelSim, Mentor Graphics Tool, OrCAD,

Operating System : Windows Family

Vlsi Programming Language : Verilog HDL

Programming Tool : Xilinx ISE Design Suite 14.5,

Designing Tool : ORCAD, Proteus

Language : C, Core Java, Embedded C

Processors : 8085 Microprocessor/8051,AVR MCU

Area of Interest:

Digital Electronics

RTL Design

Analog Electronics

Microelectronics

Advanced Vlsi design

EDUCATION

B.Tech, Electronics & Communication Engineering 2012

Marathwada Institute of Technology-Bulandshahr, Uttar Pradesh, India

M. Tech, VLSI Design 2015

Centre for development of Advanced Computing-Noida, Uttar Pradesh, India.

CERTIFICATIONS

Embedded system Training of 45 Days from DUCAT Noida.

GATE QUALIFIED-2013 and 2014

ACADEMICS PROJECTS

B.Tech Major Project

Title –Zone wise Vehicles Parameter Control System.

Abstract: This ‘Smart Zone Sensing System with Automatic Control’ system works like this. Each monitoring zones are fitted with RF Transmitter units with unique Identity Code. All the vehicles must be fitted with RF Receiver and respective circuitry on their vehicle’s number plate. Display will be fitted on the dash board for visual representation of the alert messages sent by respective zone Transmitters. Team Size: 4

M. Tech Project

M. Tech Final Year Project

Title: Design and Implementation of 3-bit Flash ADC by using MUX and GDI Technique.

Abstract: The need for a high speed and low power ADC is very essential for various applications. Flash ADCs are always the architecture choice where maximum sample rate is needed. Even though flash ADC is the fastest type available it takes enormous amount of IC real estate to implement. The main disadvantage of flash ADC is that it need large area and dissipate large amount of power. To overcome this complexity number of comparators are reducing by using multiplexers which is design with a new technique known as Gate Diffusion Input technique which reduced area of flash ADC compare to the CMOS and Transmission gate techniques. Here the multiplexers are used to generate reference voltages. A 3-bit CMOS based flash ADC is presenting, which uses reduced comparator and multiplexer based architecture. Here both the analog and the digital parts of the proposed ADC are completely modified. This architecture uses only 3 comparators for a 3 bit ADC. This 3-bit ADC is designed and simulated in Xmanager 3 with 1.8 V supply voltage and 180 nanometer technology. Team Size: 2

M.Tech Minor project

Title: Power Reduction in CMOS Circuits Using Self Controlled Stacked Transistors

Abstract: Power consumption is now a major technical problem facing the CMOS circuits. As process moves to finer technologies, leakage power significantly increases very rapidly due to the high transistor density, reduced voltage and oxide thickness. In CMOS circuits, scaling of threshold voltage results increase of sub-threshold leakage current. LECTOR is a technique for designing CMOS gates in order to reduce the leakage current without affecting the dynamic power dissipation. In our project we present the analysis for CMOS circuits such as SR FF and JK FF by implementing LECTOR technique. We implemented our project on 350nm process technology at Mentor Graphics. We have obtained significant power reduction in JK Flip Flop about 12.14%.

Team Size: 2

PERSONAL TRAITS

Flexible and Willingness to accept new challenges.

Excellent communication skills.

Disciplined.

Desire to learn and update new technologies.

HOBBIES & INTERESTS

Internet Surfing, Reading Newspapers, Playing Cricket, Making Friends etc.

DECLARATION

I hereby declare that the above-mentioned information is correct up to my knowledge and I bear the responsibility for the correctness of the above-mentioned particulars.

Place: Delhi - Yogesh Kumar

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