| Resume alert | Resumes 91 - 100 of 423 |
electrical, Auto CADD etc..
Peenya, Karnataka, India
... TECHNICAL SKILLS: EDA Tools : Cadence-Virtuoso, Xilinx ISE design suit (v14.7), Keil µVision 4 IDE, Flash Magic. Programming Language : C, MATLAB, pspice. Hardware description language : Verilog. Architectures and ALP : µC 8051. ACHIEVEMENTS: IEEE ... - 2019 Aug 07
... TECHNICAL SKILLS: EDA Tools : Cadence-Virtuoso, Xilinx ISE design suit (v14.7), Keil µVision 4 IDE, Flash Magic. Programming Language : C, MATLAB, pspice. Hardware description language : Verilog. Architectures and ALP : µC 8051. ACHIEVEMENTS: IEEE ... - 2019 Aug 07
Design Project
Koramangala, Karnataka, India
... Skill Set EDA Tools : Cadence Virtuoso, Innovus, NCLaunch, encounter, Tempus and Vivado, Cadence Orcad, ICC2 Hardware Description Languages : Verilog. Software Skills : C-Programming. Platforms : Linux, Windows. Hardware Systems : NXP ARM Cortex M3 ... - 2019 Aug 07
... Skill Set EDA Tools : Cadence Virtuoso, Innovus, NCLaunch, encounter, Tempus and Vivado, Cadence Orcad, ICC2 Hardware Description Languages : Verilog. Software Skills : C-Programming. Platforms : Linux, Windows. Hardware Systems : NXP ARM Cortex M3 ... - 2019 Aug 07
Test Cases Engineering
Bangalore, Karnataka, India
... Course Project A New Approach to Reduce Leakage Power for Low Power Design Tools Used Cadence Virtuoso Stacked keeper with body bias (SK-BB) design used to reduce static leakage reduction. Course Project Fault Analysis-Based Logic Encryption Tools ... - 2019 Jul 28
... Course Project A New Approach to Reduce Leakage Power for Low Power Design Tools Used Cadence Virtuoso Stacked keeper with body bias (SK-BB) design used to reduce static leakage reduction. Course Project Fault Analysis-Based Logic Encryption Tools ... - 2019 Jul 28
Engineering Design
Vasant Nagar, Karnataka, India
... Design Tools : TASM, CADENCE (180nm) technology. VLSI Domain Skills HDL : Verilog HVL : SystemVerilog Verification Methodologies: Coverage Driven Verification Assertion Based Verification - SVA TB Methodology : UVM Protocols : AXI, AHB, UART, I2C, ... - 2019 Apr 19
... Design Tools : TASM, CADENCE (180nm) technology. VLSI Domain Skills HDL : Verilog HVL : SystemVerilog Verification Methodologies: Coverage Driven Verification Assertion Based Verification - SVA TB Methodology : UVM Protocols : AXI, AHB, UART, I2C, ... - 2019 Apr 19
Engineer Engineering
Bangalore, Karnataka, India
... ● Software skills C Language, Xilinx ISE, Network simulator 2.35, Cadence Virtuoso, Matlab. Employment Summary United Technologies Climate, Control and Security 2018 – Current Associate Engineer UTC Climate, Controls & Security is a leading provider ... - 2019 Jan 06
... ● Software skills C Language, Xilinx ISE, Network simulator 2.35, Cadence Virtuoso, Matlab. Employment Summary United Technologies Climate, Control and Security 2018 – Current Associate Engineer UTC Climate, Controls & Security is a leading provider ... - 2019 Jan 06
Engineer Design
Bangalore, Karnataka, India
... Cadstar from Zuken–Redac Ver 2.3 & 8.0 Cadence- Allegro 15.5, 15.7, 16.2 & 16.3. Design Capture- for schematic capture. DX Designer - for schematic capture. Expedition- 5.3, 7.2, 7.8, 7.9.1 & VX.1.2. Pads VX.1.2 little bit knowledge. Completed ... - 2018 Dec 17
... Cadstar from Zuken–Redac Ver 2.3 & 8.0 Cadence- Allegro 15.5, 15.7, 16.2 & 16.3. Design Capture- for schematic capture. DX Designer - for schematic capture. Expedition- 5.3, 7.2, 7.8, 7.9.1 & VX.1.2. Pads VX.1.2 little bit knowledge. Completed ... - 2018 Dec 17
Design Engineer Power
Bangalore, Karnataka, India
... Wireless protocols- WLAN, Bluetooth, BLE, Zigbee, GSM/GPRS, GPS and SubGHz System Design and skills Schematic design using Cadence OrCAD 16.6.PCB design verification using Cadence allegro 16.6 Power supply design for board Level. Integrity analyses- ... - 2018 Dec 09
... Wireless protocols- WLAN, Bluetooth, BLE, Zigbee, GSM/GPRS, GPS and SubGHz System Design and skills Schematic design using Cadence OrCAD 16.6.PCB design verification using Cadence allegro 16.6 Power supply design for board Level. Integrity analyses- ... - 2018 Dec 09
Engineer Design
Bangalore, Karnataka, India
... Efficient Hardware Implementation of Hyperbolic Tangent and Sigmoid function-(VIVADO) Technical Tools MATLAB MULTISIM PROTUES Cadence VIRTUOSO Xilinx ISE VIVADO Advances Design System (2008) Cadence NCSIM Cadence SPB OrCAD H-Spice LT-Spice C/C++ ... - 2018 Oct 29
... Efficient Hardware Implementation of Hyperbolic Tangent and Sigmoid function-(VIVADO) Technical Tools MATLAB MULTISIM PROTUES Cadence VIRTUOSO Xilinx ISE VIVADO Advances Design System (2008) Cadence NCSIM Cadence SPB OrCAD H-Spice LT-Spice C/C++ ... - 2018 Oct 29
Embedded Systems, PCB Design, IOT
Bangalore, Karnataka, India
... read and understand the component manufacturer’s data sheets ● Proficient with C/C+ ● Proficient in Autodesk Eagle, Altium, Cadence OrCAD and Kicad tools ● Knowledge of testing power and resolving related issues ● Skilled in maintaining and creating ... - 2018 Oct 01
... read and understand the component manufacturer’s data sheets ● Proficient with C/C+ ● Proficient in Autodesk Eagle, Altium, Cadence OrCAD and Kicad tools ● Knowledge of testing power and resolving related issues ● Skilled in maintaining and creating ... - 2018 Oct 01
Engineer Project
Bangalore, Karnataka, India
... Skills Systems: Linux, Windows Languages: C, C++, VERILOG Tools: MATLAB, OrCAD, Cadence Virtuoso, Xilinx, Encounter RTL Compiler Skills: Good communication skills and Teaching skills Experience Junior Embedded Systems Engineer. QUEST INNOVATIVE ... - 2018 Sep 24
... Skills Systems: Linux, Windows Languages: C, C++, VERILOG Tools: MATLAB, OrCAD, Cadence Virtuoso, Xilinx, Encounter RTL Compiler Skills: Good communication skills and Teaching skills Experience Junior Embedded Systems Engineer. QUEST INNOVATIVE ... - 2018 Sep 24