CURRICULUM VITAE

Vinayak.G.Naik

C/o: E.S.NAIK

# ***/*, **** *****,

2nd Block Rajajinagar,

Bangalore – 10

Mobile: 988-***-**** & 827-***-****

E-Mail: ac7zo0@r.postjobfree.com

Career Objective: To obtain a responsible position in a progressive technically innovative company in the field of technical services thus utilizing and enhancing my skills for the organization benefit where my experience and analytical abilities will allow me for professional growth. Strong ability to produce results within a team environment or independently, self-motivation, and commitment

Work experience:

Worked on CAD (PCB Design): 11+ yrs.

(1)Educe Micro Research Center, Rajarajeswari Nagar, Bangalore.

Period: Jan. 1st 2006 to May 2007.

(2)ADVANCED MICRONIC DEVICES LTD, D.V.G. Road, Basavanagudi, Bangalore.

Period: June 8th 2007 to Feb 19th 2010.

Worked on-site for 2.9yrs at TEJAS NETWORKS INDIA LTD, BANGALORE.

(3)SIENNA ECAD Bangalore.

Period: March 1st 2010 to April 30th 2012.

Worked on-site for 2 months at Infinera, BANGALORE.

Worked on-site for 2 months at Intel, BANGALORE.

(4)MRO-TEK LIMITED. As a Senior PCB Design Engineer.

Period: May 29th 2012 to 31st Jan 2017.

(5)At present working as a Senior PCB Design Engineer in Wuerth Electronik PVT LTD.

Period: March 7th 2017 to till date.

Put up at Intel, BANGALORE on-site (Package designing) from June 22nd 2018 to till date.

I have designed PCB’s (multilayered boards up to 32 layers) for various PCB technologies and applications and designed boards for many customers in various domains.

Following is the break up of my technical skills:

Technical skills:

Schematic capturing, Net list and Bill of material generation.

Library creation (Symbols and foot prints)

Database creation

Board creation

Placement

Routing and cleanup

Design rule check

Gerber generation

Design Complexity:

1.Have good experience in High speed boards containing 6-40GBPS signals.

2.Worked on high speed designs that Includes DDR, DDRII, DDRIII and QDR devices.

3.Designed board up to 32 layers.

CAD packages:

Software Used:

ORCAD Capture- Ver 9.2.3 for schematic capture.

Cadstar from Zuken–Redac Ver 2.3 & 8.0

Cadence- Allegro 15.5, 15.7, 16.2 & 16.3.

Design Capture- for schematic capture.

DX Designer - for schematic capture.

Expedition- 5.3, 7.2, 7.8, 7.9.1 & VX.1.2.

Pads VX.1.2 little bit knowledge.

Completed projects:

Product: Power amp., Phatam Energy Source, & Energy Source Calibrator (2 Layers)

Design through: ZUKEN CADSTAR: 8.0

Symbol creations and schematic capture

Shape creation, board creation, placement, routing and output generation.

Board complexity- 2 layers, 500 pins frequency of 40 MHz, high component and pin density with connectors & headers. Both normal & standard line technology of 8-mil track and 8-mil clearance.

Product: Energy Source Calibrator (4 Layers)

Design through: ZUKEN CADSTAR: 8.0

Symbol creations and schematic capture

Shape creation, board creation, placement, routing and output generation.

Board complexity- 4 layers, 1k pins, frequency of 40 MHz, high component and pin density with 204 pin PQFPs Z-pack connectors and Euro connectors. Both normal & standard of 8-mil track and 8-mil clearance for digital and high reliability standards (12mil track and 12mil clearance) for analog signals used.

Product: Single Board computer [CPU CARD] (6 Layers)

Design through: ZUKEN CADSTAR: 8.0

Symbol creations and schematic capture

Shape creation, board creation, placement, routing and output generation.

Board complexity- 6 layers, 1k pins, frequency of 40 MHz, high component and pin density with DSTni-ex BGA 184 Pin, Z-pack connectors and Euro connectors. Both normal &

standard of 8-mil track and 8-mil clearance for digital and high reliability standards (12mil

track and 12mil clearance) for analog signals used.

Product: INTERFACE card (6 Layers) & SABC21E1 (8 Layers)

Design through: (Cadence) Allegro15.7

Shape creation, board creation, placement, routing.

Board complexity- 6 layers & 8 layers.

Product: TET63ME (10 Layers) & TXC8 (12 Layers)

Design through: (Cadence) Allegro15.7

Shape creation, board creation, placement, routing.

Board complexity- 10 layers & 12 layers.

Product: ELAN01 (16 Layers) & AGG20 & AGG21 (18 Layers)

Design through: (Cadence) Allegro 16.2 & 16.3.

Shape creation, board creation, placement, routing.

Board complexity- 16 layers & 18 layers.

Product: PCI to Ethernet Card:

Design through: (Cadence) Allegro 15.7.

Project Complexity: PBGA 688 pin (23 X 23MM – 0.8mm pitch)--TMS320C6457, DDR2 – MT47H64M16HR, 64bit EMI, 10/100/1000 mbps ETHERNET CHIP, 32/16 bit HPI interface.

12 layer design.

1.6mm thickness.

Length match + or – 5 Mils

Impedance control 50E, 90E and 100E differential.

Product: SDC VME,

Design through: (Cadence) Allegro 16.3.

Board Size : 233.35 x 160 MM

Layers : 10 layers

Major Components : Euro Connectors, PGA

Product: Sequoia (Blade Server)

Design through: (Cadence) Allegro 16.3.

No. Of Layer : 16 layers

Board size : 22” X 20”

Board thickness : 2.6mm

Complexity : This Board consists of 4 sandy bridge processors, 8 DIMMs two on board DDR3. Totally 8556 components & 37804 connections. Since the size of the board was huge reducing the QPI signals length was tough. The QPI signals were operating at 8GHz clock frequency and had high chance of getting effected with the Fiber wave effect. So reduce the “fiber weave effect” we have routed these signals on the 10degree angle.

Responsibility : Placement, Constraint set-up, routing, length matching.

Products: FCAT 1000UN & FCAT 1000M

Design through: Expedition- 5.3

No. Of Layer : 4 layers

Board size : 181 X 124.95 mm & 125 X 125 mm

Board thickness : 1.6mm

Complexity : This Project was a challenging and very complex design with MLF package. DDR2, Flash and RGMII are used in this Design. EMC & EMI compliance during Layout Preparation. DFM and DFT requirement.

Role & Contribution:

Interaction with Design Engineers

Library parts creation as per IPC Standards.

Understanding PCB layout guidelines.

Parts Placement, Routing and Layout completion.

DRC cleaning and Length matching

Layout Verification & Validation.

Final Gerber (Output files) preparation.

Major Constraints:

DDR placement and Routing as per PCB layout guidelines. Guidelines contains constraints details, Processor and DDR chip placement requirement, routing layers details for Address, Data groups, Clock and Length matching for all group of interfaces. Constraints Setting for placement and Routing. Mechanical construction design inputs has been checked and approved.

Gerber delivery as per company requirements.

Products: FABIO with FE & FX & FERRARI FABIO BASE BOARD

Design through: Expedition- 5.3

No. Of Layer : 2 layers

Board size : 92 X 92 mm & 110 X 84 mm

Board thickness : 1.6mm

Complexity : This Project was a challenging and very complex design to do in two layers with QFN package. Ethernet, RGMII are used in this Design. EMC & EMI compliance during Layout Preparation. DFM and DFT requirement.

Role & Contribution:

Interaction with Design Engineers

Library parts creation as per IPC Standards.

Understanding PCB layout guidelines.

Parts Placement, Routing and Layout completion.

Layout Verification & Validation.

DRC cleaning and Length matching

Final Gerber (Output files) preparation.

Product: eSONA 4 PORT CHILD CARD

Design through: Expedition- 5.3

No. Of Layer : 2 layers

Board size : 63 X 60 mm

Board thickness : 1.6mm

Complexity : This Project was a challenging and very complex design to do in two layers. Ethernet, RGMII are used in this Design. EMC & EMI compliance during Layout Preparation. DFM and DFT requirement.

Role & Contribution:

Interaction with Design Engineers

Library parts creation as per IPC Standards.

Understanding PCB layout guidelines.

Parts Placement, Routing and Layout completion.

Layout Verification & Validation.

DRC cleaning and Length matching

Final Gerber (Output files) preparation.

Products: DAISY116-IPMF-ChildCard

Design through: Expedition- 5.3

No. Of Layer : 2 layers

Board size : 171 X 90 mm

Board thickness : 1.6mm

Complexity : This Project was a challenging and very complex design to do in two layers. Ethernet are used in this Design. EMC & EMI compliance during Layout Preparation. DFM and DFT requirement.

Role & Contribution:

Interaction with Design Engineers

Library parts creation as per IPC Standards.

Understanding PCB layout guidelines.

Parts Placement, Routing and Layout completion.

Layout Verification & Validation.

DRC cleaning and Length matching

Final Gerber (Output files) preparation.

Past Work experience:

Duration: 4year & 2months in Bio-Medical field as a technical support engineer.

(1)I worked for I.R.Technology Services Pvt. Ltd. Bangalore, as technical support engineer from Jan. 2002 to Aug. 2003(1.8yrs).

(2)I worked for Unison Bio-Med Pvt. Ltd. Bangalore, as technical support engineer from Sep. 2003 to Dec. 2005 (2.4yrs).

There I was responsible for complete troubleshooting of:

MS4 – Blood Cell Counter (MS Laboratories France)

Biolyte 2000- Electrolyte Analyser (U.S.A)

CRT Series- Electrolyte/Chemistry Analyser (Nova Biomedical U.S.A)

Stat Profile Phox Series- Blood Gas/Oximetry/Electrolyte Analyser (Nova Biomedical U.S.A.)

Stat Profile Ultra Series- Blood Gas/Oximetry/Electrolyte/Chemistry Analyser (Nova Biomedical U.S.A).

Ecosys-Blood Gas Analyser (Eschweiller Germany)

Ecolyte- Electrolyte Analyser (Eschweiller Germany)

Mini-tecno- Semi Automatic Chemistry Analyser (Logo tech Italy)

Tecno168 – Semi Automatic Chemistry Analyser (Logo tech Italy)

Echo – Fully Automatic Chemistry Analyser (Logo tech Italy)

Personal details:

Father’s name: Govind V. Naik (Ex-serviceman)

Date of Birth: 11/09/1978

Marital status: Single

Nationality: Indian

Religion: Hindu

Hobbies: Playing Cricket, Traveling, Trekking, and Visiting historical places.

Permanent Address: S/O Govind V.Naik

Kumbarmakki,

Kumta-581343 (U.K)

Current Salary: 670000/- per annum

Notice Period: 3 months

Willing to be relocate: Yes.

Educational Qualification:

Completed S.S.L.C in Nirmala Convent high School Kumta.

Completed Diploma in Electronics & Telecommunication from Shree Vidyadhiraj Polytechnic College, Kumta.

Computer Knowledge:

Computer Hardware and Networking course done. (K.S.T.Mysore).

I here by declare that all the information above is correct to the best of my knowledge.

Date: 05/12/2018 Yours Faithfully

Place: Bangalore

VINAYAK.G.NAIK

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