| Resume alert | Resumes 61 - 70 of 511 |
Engineering Engineer
San Jose, CA
... Hardware languages: VHDL, Verilog, SystemVerilog, SystemC EDA tolls: Xilinx Vivado, Intel-Altera designing tools, Cadence Virtuoso Engineering software: Matlab, R Version control system: Git, SVN SUMMARY RTL Design FPGA Applications Computer ... - 2021 Jan 06
... Hardware languages: VHDL, Verilog, SystemVerilog, SystemC EDA tolls: Xilinx Vivado, Intel-Altera designing tools, Cadence Virtuoso Engineering software: Matlab, R Version control system: Git, SVN SUMMARY RTL Design FPGA Applications Computer ... - 2021 Jan 06
Engineering Program Manager
Redwood City, CA
... Manager, Systems Engineering/ODM Aug 2017 – Jun 2019 Anchor role in System Engineering as manager of outside design and manufacturing(ODM) to scale and define processes for accelerating product cadence and roll out using 3rd party engineering and ... - 2021 Jan 02
... Manager, Systems Engineering/ODM Aug 2017 – Jun 2019 Anchor role in System Engineering as manager of outside design and manufacturing(ODM) to scale and define processes for accelerating product cadence and roll out using 3rd party engineering and ... - 2021 Jan 02
Design Engineer
Union City, CA
... and yield improvement Foundation in Big data, Predictive Analytics and Machine Learning TOOLS: HSPICE, XA, SmartSpice, Cadence Virtuoso, Innovus, Tempus, QRC, Liberate, Liberate-MX, Voltus backend verification Mentor Calibre DRC,LVS, Synopsys ... - 2020 Dec 19
... and yield improvement Foundation in Big data, Predictive Analytics and Machine Learning TOOLS: HSPICE, XA, SmartSpice, Cadence Virtuoso, Innovus, Tempus, QRC, Liberate, Liberate-MX, Voltus backend verification Mentor Calibre DRC,LVS, Synopsys ... - 2020 Dec 19
Manager Program
San Jose, CA
... development, enhancement, and support projects with several technologies servicing various corporate functions Led initiative to standardize the software development process Established program level cadence and drive program level ceremonies (e.g. ... - 2020 Dec 15
... development, enhancement, and support projects with several technologies servicing various corporate functions Led initiative to standardize the software development process Established program level cadence and drive program level ceremonies (e.g. ... - 2020 Dec 15
Design Engineering
San Jose, CA
... Logic Synthesis, UVM testbench Development., Synopsys VCS, Quartus prime, Mentor graphics Model Sim, Xilinx ISE/ Vivado HLS, Cadence Virtuoso, GTK wave., debugging, Digital circuit Design, RTL coding, schematic, Eclipse IDE, Spring Boot, Postman. • - 2020 Dec 10
... Logic Synthesis, UVM testbench Development., Synopsys VCS, Quartus prime, Mentor graphics Model Sim, Xilinx ISE/ Vivado HLS, Cadence Virtuoso, GTK wave., debugging, Digital circuit Design, RTL coding, schematic, Eclipse IDE, Spring Boot, Postman. • - 2020 Dec 10
Salesforce Program Manager/Digital Transformation/Business Application
Palo Alto, CA
... 75% shift in customer feedback from acceptance testing to earlier development phase due to active engagement on a regular cadence, resulting in shorter delivery time. 40% improvement in team performance owing to agile transformation. 80% drop in ... - 2020 Nov 04
... 75% shift in customer feedback from acceptance testing to earlier development phase due to active engagement on a regular cadence, resulting in shorter delivery time. 40% improvement in team performance owing to agile transformation. 80% drop in ... - 2020 Nov 04
Engineer Manager
San Jose, CA
... EducatioN ●NATIONAL UNIVERSITY, San Jose, CA - Bachelor of Science in Computer Science 1999 ●UNIVERSITY OF CALIFORNIA, Los Angeles, CA - Bachelor of Science in Biochemistry 1997 ●Cadence Management Corporation, San Jose, CA - 16 hours of Project ... - 2020 Oct 30
... EducatioN ●NATIONAL UNIVERSITY, San Jose, CA - Bachelor of Science in Computer Science 1999 ●UNIVERSITY OF CALIFORNIA, Los Angeles, CA - Bachelor of Science in Biochemistry 1997 ●Cadence Management Corporation, San Jose, CA - 16 hours of Project ... - 2020 Oct 30
Sr. Electrical Engineer Design
Campbell, CA
... Debugging and EDVT test of Cadence Z1 product, Klingon products and VolcanP products. Debugging and test of 100Gbps Ethernet CISCO products. Design and development of 10Gbps Ethernet products including network processors and switching devices. ... - 2020 Oct 23
... Debugging and EDVT test of Cadence Z1 product, Klingon products and VolcanP products. Debugging and test of 100Gbps Ethernet CISCO products. Design and development of 10Gbps Ethernet products including network processors and switching devices. ... - 2020 Oct 23
Inside Sales Manager
San Jose, CA
... Created Outbound calling cadence for lead and key account follow up. Managed an ABM structure focusing on Health systems with over 250 million in revenue. Netbase – 12/2014 – 4/2016 Director, Inside Sales Developed and managed a team of 10. ... - 2020 Oct 02
... Created Outbound calling cadence for lead and key account follow up. Managed an ABM structure focusing on Health systems with over 250 million in revenue. Netbase – 12/2014 – 4/2016 Director, Inside Sales Developed and managed a team of 10. ... - 2020 Oct 02
Design Engineering
San Jose, CA
... Simulation tools: Synopsys VCS, PrimeTime, Cadence NC-Verilog, DVE waveform viewer, Xilinx Vivado, Quartus 2, Git. Relevant concepts: SystemVerilog Assertions (SVA), Functional Coverage, Constraint Random Verification. ACADEMIC PROJECTS: Functional ... - 2020 Aug 05
... Simulation tools: Synopsys VCS, PrimeTime, Cadence NC-Verilog, DVE waveform viewer, Xilinx Vivado, Quartus 2, Git. Relevant concepts: SystemVerilog Assertions (SVA), Functional Coverage, Constraint Random Verification. ACADEMIC PROJECTS: Functional ... - 2020 Aug 05