408-***-**** (m)

aditio@r.postjobfree.com

SUMMARY

Microprocessor, SRAM, Clock, Physical Design, SoC, Statistical Design, Machine Learning, Business Analytics

Rich, diverse experience in high performance, low power, and high-yield microprocessor designs in cutting edge deep submicron FinFET technologies with passion for statistical design techniques

Effectively used innovation, collaboration, and automation to efficiently deliver complex designs on schedule with great quality

Great problem solving, documentation and communication skills

Proven track record of meeting aggressive schedules with high quality deliverables for 9 generations of SPARC CMT microprocessors

COMPETENCIES

Microprocessor SRAM array Register File, CAM design for high performance microprocessors

Clock design expertise for high performance, low power and low skew clocks

Semi-Custom Place and Route design for complex embedded logic in custom SRAMs

Timing margin methodology development with AOCV / POCV

Deep knowledge of CMOS planar and FINFET technologies for 10nm / 7nm designs

Expertise on layout dependent effects (LDE) to improve circuit performance and robustness

Cross domain, multi VDD design expertise for DVFS, SoC designs

Memory Complier based design expertise

Statistical design methodology and automation for memory bitcell analysis, circuit design optimization, sensitivity analysis, self timed race margins, flop hold margin characterization and yield improvement

Foundation in Big data, Predictive Analytics and Machine Learning

TOOLS: HSPICE, XA, SmartSpice, Cadence Virtuoso, Innovus, Tempus, QRC, Liberate, Liberate-MX, Voltus backend verification Mentor Calibre DRC,LVS, Synopsys StarRC, ICC, Primetime, Statistical Analysis tool JMP, MATLAB, R, Alteryx, Tableau, Perl, Python, shell

PROFESSIONAL EXPERIENCE

Cadence Design Systems 2019 – Present

Sr. Principal Solutions Engineer

Enabling and enhancing Digital Sign Off design solutions and solving design challenges in cutting edge latest technologies to help deliver the pioneering designs on Tempus, Voltus, Innovus, Clarity, and Celsius sign off platforms.

Spin Memory 2018 – 2019

Principal Hardware Engineer

MRAM Endurance Engine Cache Design

CMOS SRAM / CAM Circuit design with Digital Logic Implementation of cache pipeline.

Hands on experience on Cadence Tools such as Spectre, LEC, Tempus, Innovus, Voltus, Liberate,Liberate MX and Quantus for logic verification, timing characterization, RC extraction, Spice simulation and EMIR electrical analysis

Micron Technology 2018 – 2018

Principal Member of Technical Staff

NAND Flash Design and Development

Design and validation on data path, mixed-signal circuitry and high-speed I/O interfaces of Flash Memory (nonvolatile memory) products

Perform simulations covering the read, program, and erase operations of the NAND flash product

Design and execute experiments to characterize the response of read margins, RWB, performance, reliability, and manufacturing yield

Oracle Corp. 2010 –2018

Principal Hardware Engineer

SRAM Array Design

Designed SRAMs for high performance multi-port register files and CAM arrays

Pioneered methodologies for efficient custom circuit variation aware designs in deep-submicron design for SRAMs and register files and CAMs including feasibility of micro-architecture, timing, margins simulation, layout planning, physical backend and functional verification, design sign-off

Clock Design

Designed and tuned clock grid for high performance low skew, low power microprocessor, reducing clock power by 30% with minimum penalty (< 0.2ps) on clock skew

Formulated clock skew budgets for max / min architectural critical path timing closures

SoC Physical Design

Designed low voltage timing margin methodology for wire dominated data paths min time closure

Established and automated the proven and working spice margin methodology, reducing pessimism in the design margins for low voltage, cross domain SoC design for DVFS applications. CDC and UPF familiarity

Expertise in Floor planning, place and route, power grid, STA using Synopsys and Mentor Tools

AOCV / POCV Timing Methodology

Pioneered, established, and automated min timing margin methodology for high performance critical timing paths, replacing a fixed de-rate margin with input slew, output load, logic depth, position in the logic path, distance from the common node and operating voltage, temperature conditions

Reduced pessimism, enabling easier and faster timing closure on min time critical top CPU timing paths

Designed compiler based memories and familiar with the memory compiler concept, design approach and applications for fast turnaround of configurable memories

Designed semi-custom sub-blocks in the complex memory using place and route for the data paths and the control blocks and custom logic in memories reducing turnaround time

Statistical Design & Analysis

Delivered core expertise on statistical design methods and techniques with Monte Carlo analysis, designing and optimizing (DOE) robust circuits to mitigate design variability for SRAMs and microprocessors with high yield to meet challenges for latest technologies

Trailblazed, pioneered and successfully led formulated and established Statistical design methodologies using statistical design expertise enabling high quality, high yield circuit designs

Established these methodologies to meet design specifications with low risk, high yield, and high quality to help meet aggressive design schedule by judging the risk assessment, mitigating impact of process variability and removing pessimism to meet design goals

Pioneered, implemented and automated statistical design methodologies for memory cell design, flop characterization and yield analysis, clock skew analysis, design sensitivity and optimization using DOE, self-timed margins, leaker-keeper design, noise budgets etc. improving performance, quality and robustness of the designs

Mentored engineers, helping them become more proficient in statistical design techniques

Process and Technology

Studied process and technology issues for planar and 10nm / 7nm Finfet technology to formulate design guidelines

Understanding and usage of Layout Dependent Effects, improving design performance

Developed physical based statistical models for high performance aggressive designs, enabling better understanding and use of design variation

Contributed great knowledge of NBTI / PBTI transistor aging and impact on designs and methodologies

Performed analysis and methodology for optimum contact coverage on transistors for optimum performance

SUN Microsystems 1997 – 2010

Staff Hardware Engineer

High performance clock design for low skew, low power microprocessors

Designed SRAMs for high performance multi-port register files and CAM arrays

Worked on the memory compiler based designs and familiar with the memory compiler concept, design approach and applications

Worked on semi-custom place and route for the data paths and the control blocks and custom logic in memories

Pioneered and established Statistical Design methodology for SUN microelectronics

PREVIOUS EXPERIENCE

Sr. Design Consultant, Cadence Design Spectrum Services Group, San Jose, CA 1996 – 1997

Memory Design Engineer, ST Microelectronics, New Delhi, India 1994 – 1996

ASIC Design Engineer, DCM Microelectronics, New Delhi, India 1991 – 1994

EDUCATION

BE, Electronics and Communication Engineering, Delhi College of Engineering, India, 1987 – 1991

CORe, Credential for Readiness in Business Analytics, Economics for Managers, and Financial Accounting, HBX, Harvard Business School 2017

Business Analytics Nanodegree - Udacity 2017

Certification - Machine Learning, Stanford University 2017

Certification – Business Analytics – Wharton Business School 2018

AWARDS & HONORS

National Merit award and scholarship from Indian Govt. for academic excellence in high school

14 US patents for SRAMs and register file designs

Register file read design scheme for high performance and low power design

High performance address decoding techniques

Efficient method of data transfer between register files

Method and pipeline for performing multiple swap requests to reduce the latency

Adaptive timed keeper control mechanism to reduce leakage and help writability.

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