| Resume alert | Resumes 141 - 150 of 510 |
Design Engineer Professional Experience
San Jose, CA
... Expertise includes Place & Route design automation utilizing ICC & TCL scripts for ASIC physical implementation, automated design library/collateral view generation using ICC and Cadence Virtuoso, block-level and chip-level layout verification using ... - 2017 Dec 21
... Expertise includes Place & Route design automation utilizing ICC & TCL scripts for ASIC physical implementation, automated design library/collateral view generation using ICC and Cadence Virtuoso, block-level and chip-level layout verification using ... - 2017 Dec 21
ASIC Verification Engineer, NVIDIA
San Jose, CA, 95134
... C++ STL, MPI, OpenGL, pThreads, Linux, GNU Toolchain (gdb, awk, sed, Make, etc.) Tools CUDA, ns-2, pSpice, EagleCAD, GNU Radio, Cadence Virtuoso Design and Verification VCS, Verdi, ModelSim, UVM, DPI-C, PLI, C-models for Verification, Fullchip/SoC ... - 2017 Dec 12
... C++ STL, MPI, OpenGL, pThreads, Linux, GNU Toolchain (gdb, awk, sed, Make, etc.) Tools CUDA, ns-2, pSpice, EagleCAD, GNU Radio, Cadence Virtuoso Design and Verification VCS, Verdi, ModelSim, UVM, DPI-C, PLI, C-models for Verification, Fullchip/SoC ... - 2017 Dec 12
Design Electrical Engineering
San Jose, CA
... MPLAB IDE, LTpower Play, multi-meter, Optical Spectrum analyzer, Logic analyzer Electronic Design Tools: Synopsys VCS, NCVerilog, Design Compiler, Altera Quartus II, Cadence Virtuoso, Cadence Encounter, Cadence Allegro Physical Viewer, ModelSim. ... - 2017 Dec 06
... MPLAB IDE, LTpower Play, multi-meter, Optical Spectrum analyzer, Logic analyzer Electronic Design Tools: Synopsys VCS, NCVerilog, Design Compiler, Altera Quartus II, Cadence Virtuoso, Cadence Encounter, Cadence Allegro Physical Viewer, ModelSim. ... - 2017 Dec 06
Program Manager, UX Designer
San Jose, CA
... - Running XRC, XCC, and Power Extrac on, by using the extrac on program in cadence, helped the circuit engineers with changes in circuits. - Knowledge of device op miza on, minimizing parasi cs, component matching, including techniques to minimize ... - 2017 Dec 02
... - Running XRC, XCC, and Power Extrac on, by using the extrac on program in cadence, helped the circuit engineers with changes in circuits. - Knowledge of device op miza on, minimizing parasi cs, component matching, including techniques to minimize ... - 2017 Dec 02
Engineer Manager
San Jose, CA
... • Jan 2002 – July 2003 Senior Architect, Cadence Design Systems, Inc.. Austin, TX Telecommuting from Austin. Working on the interface between Open Access and ‘First Encounter’ floorplanner. Patent awarded for Genesis database technology # 6,529,913. ... - 2017 Nov 28
... • Jan 2002 – July 2003 Senior Architect, Cadence Design Systems, Inc.. Austin, TX Telecommuting from Austin. Working on the interface between Open Access and ‘First Encounter’ floorplanner. Patent awarded for Genesis database technology # 6,529,913. ... - 2017 Nov 28
Electrical Engineering Design
Cupertino, CA
... Control aspects of the RAM were verified using system Verilog assertions TECHNICAL SKILLS Programming Languages: Verilog, Perl, Python, C, C++, UVM, System Verilog Tools Used: Vivado HLS, Synopsys VCS, Formality, Cadence Virtuoso, Mentor Graphics IC ... - 2017 Nov 22
... Control aspects of the RAM were verified using system Verilog assertions TECHNICAL SKILLS Programming Languages: Verilog, Perl, Python, C, C++, UVM, System Verilog Tools Used: Vivado HLS, Synopsys VCS, Formality, Cadence Virtuoso, Mentor Graphics IC ... - 2017 Nov 22
Manager Designer
San Jose, CA
... & Flex Cable, Using Cadence Allegro 16.6. OCZ Storage Solutions, San Jose, CA (Contract) Dec 14 – Mar 15 CAD/PCB Librarian & Layout Designer Responsibilities: 1Maintain ownership of CAD libraries and insure synchronicity, Design Layout of 4 - 10 ... - 2017 Oct 31
... & Flex Cable, Using Cadence Allegro 16.6. OCZ Storage Solutions, San Jose, CA (Contract) Dec 14 – Mar 15 CAD/PCB Librarian & Layout Designer Responsibilities: 1Maintain ownership of CAD libraries and insure synchronicity, Design Layout of 4 - 10 ... - 2017 Oct 31
Design Electrical Engineering
Sunnyvale, CA
... 7/4.0 Aug 2009 - July 2013 TECHNICAL SKILLS Programming languages : C, C++, Verilog, Perl, Python, System Verilog EDA Tools: Cadence Virtuoso, Cadence NCSim, Cadence SOC Encounter, Synopsys Design Compiler, Cadence Conformal LEC, Synopsys PrimeTime, ... - 2017 Oct 26
... 7/4.0 Aug 2009 - July 2013 TECHNICAL SKILLS Programming languages : C, C++, Verilog, Perl, Python, System Verilog EDA Tools: Cadence Virtuoso, Cadence NCSim, Cadence SOC Encounter, Synopsys Design Compiler, Cadence Conformal LEC, Synopsys PrimeTime, ... - 2017 Oct 26
Electrical Engineering Engineer
San Jose, CA
... (Electrical Engineering), 2016 TECHNICAL SKILLS Software Skills: C, C++, Java, MATLAB, Xilinx (VHDL), LabVIEW, MIPS, Logicworks, PSpice, Logisim, Cadence 5, Cadence 6, JDSP, Spotfire Hardware Skills: FPGA design basics, basic circuit building on ... - 2017 Oct 23
... (Electrical Engineering), 2016 TECHNICAL SKILLS Software Skills: C, C++, Java, MATLAB, Xilinx (VHDL), LabVIEW, MIPS, Logicworks, PSpice, Logisim, Cadence 5, Cadence 6, JDSP, Spotfire Hardware Skills: FPGA design basics, basic circuit building on ... - 2017 Oct 23
Embedded System Engineer
San Jose, CA
... Can Design PCB Layouts and simulate/debug the same in Multisim, Altium, Proteus, Cadence Capture/PSpice. Analog and Digital Hardware Designer. Can quickly learn and master any new software/hardware in a short duration. Possess good communication ... - 2017 Oct 12
... Can Design PCB Layouts and simulate/debug the same in Multisim, Altium, Proteus, Cadence Capture/PSpice. Analog and Digital Hardware Designer. Can quickly learn and master any new software/hardware in a short duration. Possess good communication ... - 2017 Oct 12