| Resume alert | Resumes 151 - 160 of 450 |
Design Engineer Electrical Engineering
Santa Clara, CA, 95050
... Skills: Web Technologies: HTML/CSS/JavaScript, XML, JSON Programming Languages: C/C++, Python, Java, Matlab, SQL, Verilog Platforms: Windows, Linux and Mac OS X Tools: Eclipse, Altera Quartus, Xilinx Vivado, Visual Studio, Github, Sublime Text ... - 2017 May 29
... Skills: Web Technologies: HTML/CSS/JavaScript, XML, JSON Programming Languages: C/C++, Python, Java, Matlab, SQL, Verilog Platforms: Windows, Linux and Mac OS X Tools: Eclipse, Altera Quartus, Xilinx Vivado, Visual Studio, Github, Sublime Text ... - 2017 May 29
Design Engineer Electrical Engineering
Santa Clara, CA
... Devise common Verilog-A Flash corecell for full-chip/macro shortening verification cycle from 2 weeks to 3 days for the design team. Redesign low power 300MHz multi-mode SDR/DDR2 circuits for compatible NAND industry standard interface (ONFI) in 1 ... - 2017 May 18
... Devise common Verilog-A Flash corecell for full-chip/macro shortening verification cycle from 2 weeks to 3 days for the design team. Redesign low power 300MHz multi-mode SDR/DDR2 circuits for compatible NAND industry standard interface (ONFI) in 1 ... - 2017 May 18
Software Engineer State University
San Jose, CA
... Jose (GPA 3.5) Aug 2015 – May 2017(Expected) • Bachelor of Engineering, Electronics and Communication at Visvesvaraya Technological University July 2014 COMPETENCIES: Programming/Scripting Languages: C, C++, Java, Python, Verilog, XML, HTML, CSS. ... - 2017 May 14
... Jose (GPA 3.5) Aug 2015 – May 2017(Expected) • Bachelor of Engineering, Electronics and Communication at Visvesvaraya Technological University July 2014 COMPETENCIES: Programming/Scripting Languages: C, C++, Java, Python, Verilog, XML, HTML, CSS. ... - 2017 May 14
Electrical Engineering Design
Milpitas, CA, 95035
... • Micro wind: for VLSI design, VERILOG coding • Automation: PLC Programing, HMI design. • Operating system: Windows, UNIX, Linux. • Matlab: coding, Simulation, Image processing • Programing languages: C, C++, java Work History Carl Zeiss Inc. – ... - 2017 May 11
... • Micro wind: for VLSI design, VERILOG coding • Automation: PLC Programing, HMI design. • Operating system: Windows, UNIX, Linux. • Matlab: coding, Simulation, Image processing • Programing languages: C, C++, java Work History Carl Zeiss Inc. – ... - 2017 May 11
Design Electrical Engineering
San Jose, CA
... • Verilog, System Verilog, VHDL, power and performance analysis, computer architecture, and CMOS VLSI design. • SCAN, SoC bus protocols, SoC bus arbitration schemes, place and route, layout design, and floor planning. • Design verification, test ... - 2017 May 06
... • Verilog, System Verilog, VHDL, power and performance analysis, computer architecture, and CMOS VLSI design. • SCAN, SoC bus protocols, SoC bus arbitration schemes, place and route, layout design, and floor planning. • Design verification, test ... - 2017 May 06
Electrical Engineering Engineer
San Jose, CA
... Verilog Hardware: PSoC (Programmable System on Chip): PSoC 5, PSoC 3, PSoC 3, MBed FRDM boards; Arduino UNO board Tools: Advanced Design Software ADS; MATLAB; Eagle; Proteus Simulation; PSoC Creator; Altium; NS3; Wireshark; LaTeX; MS Word, MS ... - 2017 Apr 22
... Verilog Hardware: PSoC (Programmable System on Chip): PSoC 5, PSoC 3, PSoC 3, MBed FRDM boards; Arduino UNO board Tools: Advanced Design Software ADS; MATLAB; Eagle; Proteus Simulation; PSoC Creator; Altium; NS3; Wireshark; LaTeX; MS Word, MS ... - 2017 Apr 22
Hardware Engineer
San Jose, CA
... aczxag@r.postjobfree.com https://www.linkedin.com/in/sindhumaturi Summary Proficiency in HDL coding such as Verilog, VHDL and good programming skills in C, C++ and python. Experience with simulation, schematic and layout design tools like Cadence ... - 2017 Apr 21
... aczxag@r.postjobfree.com https://www.linkedin.com/in/sindhumaturi Summary Proficiency in HDL coding such as Verilog, VHDL and good programming skills in C, C++ and python. Experience with simulation, schematic and layout design tools like Cadence ... - 2017 Apr 21
Physical Design Engineer
San Jose, CA
... Design on Programmable Devices Computer Architecture SKILLS SET Programming Languages : Verilog HDL, Perl, Tcl, C, System Verilog, C++ Tools : Synopsys Design Compiler, Vivado, ICC2, Innovus, Prime time, Synopsys Formality Mentor Graphics Calibre. ... - 2017 Apr 14
... Design on Programmable Devices Computer Architecture SKILLS SET Programming Languages : Verilog HDL, Perl, Tcl, C, System Verilog, C++ Tools : Synopsys Design Compiler, Vivado, ICC2, Innovus, Prime time, Synopsys Formality Mentor Graphics Calibre. ... - 2017 Apr 14
Design Engineer Data
Newark, CA, 94560
Chih Kao (Jack) Hsieh aczr8h@r.postjobfree.com www.linkedin.com/in/chihkao-jack-hsieh Current address: Fremont, CA, 94555 707-***-****(C) 408-***-**** Senior FPGA/ASIC Design/Verification Engineer Technical skill Technical experience: 1.Verilog/VHDL ... - 2017 Apr 12
Chih Kao (Jack) Hsieh aczr8h@r.postjobfree.com www.linkedin.com/in/chihkao-jack-hsieh Current address: Fremont, CA, 94555 707-***-****(C) 408-***-**** Senior FPGA/ASIC Design/Verification Engineer Technical skill Technical experience: 1.Verilog/VHDL ... - 2017 Apr 12
Software Engineer, C++,Python, Middleware Technologies
Fremont, CA
... •Hands-on experience in C, C++, Python and Verilog. EDUCATION: M.S., Computer Engineering San Jose State University GPA 3.7 Dec 2017 [Expected] B.E., Telecommunication Engineering Visvesvaraya Technological University GPA 3.6 Jul 2012 RELEVANT ... - 2017 Apr 10
... •Hands-on experience in C, C++, Python and Verilog. EDUCATION: M.S., Computer Engineering San Jose State University GPA 3.7 Dec 2017 [Expected] B.E., Telecommunication Engineering Visvesvaraya Technological University GPA 3.6 Jul 2012 RELEVANT ... - 2017 Apr 10