Physical Design Engineer

PRAGNESH KUMAR VAJRAM Email: *******************@*****.***

***** ******* ***** **, *** Diego, CA-92130 Phone: 408-***-**** https://www.linkedin.com/in/pragnesh-vajram-51986085 PROFILE SUMMARY:

• Hands on experience in Implementing entire Physical Design flow from netlist to GdsII.

• Hands on experience with Timing closure using primetime for high-speed digital blocks.

• Hands on experience in Physical verification that involves Drc, lvs, Erc, Pattern matching, Antenna issues and IR Drop fixes.

• Hands on experience on conformal tool and working knowledge on Scan insertion.

• Good communication skills, coordinate and work as a team. WORK EXPERIENCE

Qualcomm Inc (ASIC Physical Design Engineer) (Mindlance Inc) Oct 2016 - Present

• Involved in implementing Blocks with multi voltage domains from netlist to GdsII in 10lpe finfet Technology.

• Worked with the logic design team to update timing constraints required for implementation.

• The clock frequency targeted is 1.25 Ghz and the block’s has more than 750k instances.

• Worked with signoff team to achieve timing closure and PV clean up for the Base and Metal Tape out. Qualcomm Inc (ASIC Physical Design Intern) June 2015 – Sep 2015

• Developed and provided Perl scripts for Physical Design Team. Worked on automating the flow by processing the log files in reporting extracted and missing corner libs from library models.

• Worked on Encounter tool for Pin and memory placement. SmartPlay Inc (ASIC Physical Design Intern) Aug 2013 – April 2014

• Worked on physical implementation from floorplan, placement, CTS and routing on digital logic blocks.

• Understanding of memory grouping and congestion analysis.

• Worked on static timing analysis on digital logic blocks.

• Analyzing the design, recognizing the critical paths, fixing timing violations and reporting them. EDUCATION

Santa Clara University Sep 2014 - June 2016

Masters Degree In Electrical Engineering GPA: 3.84/4 Vellore Institute Of Technology June 2010 – May 2014 Bachelors Degree In Electronics and Communication Engineering GPA: 3.8/4 Relevant course work:

VLSI Design – 1 VLSI Design - 2 Logic Analysis and Synthesis Modern Timing Analysis VLSI Physical Design SOC Formal Verification Independent study on UVM Semi Custom Design on Programmable Devices

Computer Architecture

SKILLS SET

Programming Languages : Verilog HDL, Perl, Tcl, C, System Verilog, C++ Tools : Synopsys Design Compiler, Vivado, ICC2, Innovus, Prime time, Synopsys Formality Mentor Graphics Calibre.

Operating Systems : Windows, Linux, Mac OS

ACADEMIC PROJECTS

• SOC Formal Verification – Bluetooth Baseband

Simulated and synthesized Bluetooth Baseband Data Layer Transmitter and verified its functionality for both block level and sub-block modules using system Verilog assertions and Functional coverage points. Using the formality tool equivalence checking was successfully done between RTL and netlist.

• RTL Design of Single Cycle Datapath of 32-bit MIPS Processor Designed a single cycle datapath for R, I and J type of instruction formats and implemented it using Verilog. A detailed test plans were developed to test the functionality and for whole IP implementation.

• Semi Custom Design of 8x8 Internet Router on Programmable Devices (FPGA) Designed and verified the functionality of an 8x8 Internet switch in Verilog and synthesized the design using Design Compiler to ensure that they are no latches and race conditions and later synthesized the design on Xilinx implementation tool Vivado targeting ZYBO 7000 series FPGA which is encored with 28,000 logic cells.

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