GARRY TSE

ac0dmz@r.postjobfree.com ● 510-***-****

INTEGRATED CIRCUIT DESIGN ENGINEER

Self-motivated, innovative IC Design Engineer with proven experience in analog mixed-signal circuit designs and in depth knowledge of deep submicron semiconductor device physics. With resourceful and adaptive problem- solving mindset, easy going attitude helps mentoring peer/junior engineers. Enthusiastic about leading-edge technology advances. Unique combination of skills in:

Analog/Mixed-signal CMOS/FinFET Devices Circuit Simulation

NOR/NAND Flash SOC / ASIC CAD

DDR/DDR2 I/O Parasitic Extraction DRC/LVS/ERC TECHNICAL SUMMARY

Spectre/APS XPS/Ultrasim Eldo Finesim/FinesimPro

Hspice/Hsim Calibre/Hercules QRC/StarRC Encounter/Innovus

ETS Virtuoso/SKILL RedHawk Design/RTL Compiler

ICF 10nm/7nm VXL Placer/Router Perl/Tcl/Ruby C-shell/Bourne/Linux PROFESSIONAL EXPERIENCE

Intel (Santa Clara, CA) 2017-Present

CAD Engineering III (Contractor)

Team member of the Intel Custom Foundry. Develop analog / mixed-signal circuit design flow for 10nm/7nm FinFET deep sub-micron with industry standard semiconductor CAD design tools.

Develop circuit design reference flow using Intel in-house CAD utilities and Cadence/Synopsys/Mentor IC design tools, such as Spectre/Hspice/Virtuoso/Calibre/Redhawk.

Publish custom design flow documents for Intel internal and outside customers.

Work with CAD development team to enhance Intel CAD utilities and suggest new utilities to optimize design cycles.

Develop CAD tools to streamline the design flow with Perl/SKILL scripts.

Correlate simulation data with foundry design documents. Cypress Semiconductor (San Jose, CA) 2010 – 2016

Senior Staff Electrical Design Engineer

Team member of the Flash Memory Design. Develop analog circuits for Flash memory in 32/45/65nm technologies, including NOR/3D-NAND technologies, resolve unexampled circuit issues, research new circuit checks, and mentor junior engineers.

Develop analog/digital circuits and run simulations with Cadence Spectre/APS/XPS/Ultrasim and Synopsys Hspice within the 2 months schedule.

Devise common Verilog-A Flash corecell for full-chip/macro shortening verification cycle from 2 weeks to 3 days for the design team.

Redesign low power 300MHz multi-mode SDR/DDR2 circuits for compatible NAND industry standard interface

(ONFI) in 1 week rather than 2 weeks regular schedule.

Construct high speed NAND Flash memory SDR/DDR2 datapath circuits and ADE-XL PVT simulation test-benches.

Implement and simulate PVT ultra-high voltage analog macros, i.e. charge-pumps, voltage references, internal oscillators within proposed 1 month deadline.

Automate verifications of foundry spice models and PDK in Cadence ADE-XL for Modelling group cutting down release time from 3 weeks to 3 days.

Write Perl scripts for functional verifications in memory data bitmap read/write pattern reducing turnaround time from 2 days to 1 hour.

Write Perl/SKILL codes to automate standard cell libraries scaling and parameter changes for various technology nodes

(32/45/65nm) shortening development schedule from 3 weeks to 4 days.

Automate ERC CAD flow to verify multi-voltage domain for various operation modes from 2 days to 2 hours. GARRY TSE ac0dmz@r.postjobfree.com ● 510-***-**** P A G E 2

Innovate proprietary hierarchical ERC (HERC) for full-chip Flash memory designs and scaled down completion time from 3 months to 2 days. (The whole process was published in “Cadence CDNLive 2013” paper) Member of Technical Staff ASIC Engineer (formerly Spansion) 2010 – 2014

Team member of the Flash Memory CAD. Main mixed-signal circuit simulator liaison to CAD vendors, developed simulation/extraction flow for Flash designs in 45/65/90nm technologies, evaluated/enhanced analog simulation/extraction/rule-check tools, resolved unprecedented circuit simulation issues, formulated unprecedented industry static/dynamic circuit checks.

Launched 32/45/65/90nm Flash memory simulation flows with Cadence ADE setups for simulators Spectre/APS/XPS/Ultrasim/Finesim.

Optimized various simulator runtimes from 1 week maximum down to 1.5 days (80% less) with smaller database size and better waveform accuracy.

Established device spice model availability/characterizations/performance methodologies with simulators/Perl/SKILL within 3 days (10 times faster).

Developed debugging mechanisms for high voltage circuits with post-layout and extracted data to help designers to narrow the critical loading and early discovery of functional failures (no more revision).

Wrote Perl scripts to analyze/filter large amount (GBytes of data) of chip level parasitic extraction coupling effects on high-speed/high-voltage/sensitive signals, taking only 1/3 of the 1 week schedule.

Coordinated with Cadence to build/debug block level simulation setups for critical analog signals with parasitic effects, pin-pointed layout discrepancies before final layout release, cutting debug time from 1 week to 3 days.

Cooperated with Cadence to construct custom chip level simulation flow with parasitic to verify functional operations, critical delays were identified/corrected 5 times quicker.

Incorporated full-chip/macro optimal simulation methodologies (less data/better accuracy/less runs) with simulators

(Spectre/APS/Finesim/XPS/ Ultrasim/FinesimPro with more complex custom foundry spice models).

Cooperated with Model group to develop propriety Flash memory Verilog-A core-cell models to reduce simulation run- time by 30% with non-converging spice models.

Innovated/tuned custom in-house high-voltage ERC / device characterization tools with Cadence ADE-XL.

Initiated Perl/Tcl/Shell scripts for design group to dispatch simulation runs to server farm for batch runs.

Released/documented all simulation specifications for all global sites, including Japan/Israel/Malaysia/China.

Configured all global sites full-chip/sub-block circuit simulations with 5 times better performance (less data/fast runtime).

Teamed with Technology group to characterize custom Monte Carlo simulation requirements.

Closely worked with CAE vendors for all simulator functional problems and new features/versions, performance comparisons with Flash designs, the runtimes was at least 5 times better (Cadence press release 10-May-2016).

Innovated with CAE vendors to debug/optimize/propose new ERC/simulation features to provide thorough dynamic circuit analyses, eliminating 60% of duplicated errors/warnings.

Proposed new mixed-signal sub-block simulation methodologies with hierarchical approach to CAE vendors (Synopsys SNUG 2013 paper), drastically slashing the verification time from 3 weeks to 3 days. Nethra Imaging (Santa Clara, CA) 2009 – 2010

Senior Staff Engineer / Silicon Technology

Team member of the Silicon Technology Group. Managed all foundry matters (TSMC/UMC) for multiple 90nm SOC designs. Managed/evaluated/compared all IP’s from vendors for their power/area/performance. Completed all 3 90nm SOC tapeout processes with successful silicons.

Analyzed/compared 28/40/65nm low-power/low-leakage SOC power management circuits, documented the performance comparisons to management and implemented the SOC designs within 2 months schedule.

Oversaw SOC’s multiple power domain power analyses, signal integrity and functional verification.

Documented the SOC package limitations and recommended the most reliable BGA package.

Analyzed high-speed I/O sub-LVDS/LVDS from different vendors and selected the best IP for SOC’s.

Customized/automated full-chip schematic and physical verification tools to expedite the design cycles, shortening the tapeout time within 2 days (4 times faster and saving $500K engineering costs).

Administered on 45/65/90nm high-speed graphic processing interfaces (3GHz+ channels), and low power circuit (I/O, logics) optimizations within 2 weeks schedule.

Incorporated Cadence RC for low-power/high-speed logic synthesis and ETS timing analyses to benchmark standard cell libraries from multiple foundry vendors.

Assisted logic team on ETS for post-layout SDR timing analyses for some logic blocks. GARRY TSE ac0dmz@r.postjobfree.com ● 510-***-**** P A G E 3

Co-ordinated with foundry vendors on spice models and RDL bump package specifications.

Worked with packaging houses and substrate design services to complete the SOC packaging requirements within 3 weeks (rather than proposed 2 months), shortening the SOC floor-planning schedule.

eviewed critical signal routings on bump mounting substrates, especially GHz signals, within 2 weeks.

Worked with design team on chip-level integration and ran spice simulations of PCIe (5GHz), XAUI (6GHz), DDR3(1.2GHz), LVDS/subLVDS transceivers.

Constructed and characterized broad level chip-to-chip XAUI and PCIe interconnects.

Simulated/reported timing/power analyses of embedded SRAM/DLL/PLL/SERDES within 2 weeks and proposed the enhanced power grids for better noise immunity.

Performed full-chip ESD analyses, debugging and enhancements.

Guided I/O vendors to fix the I/O IP ESD discrepancies and verified with silicon results within 3 weeks.

Resolved chip/module-level DRC/LVS/ANT/ERC in Calibre and Hercules with multiple IP vendors, cutting down the final full-chip physical verification runtimes to 2 days and had minimal delay for mask releases.

Analyzed/documented I/O SI/power/drive-strength for different package models.

Automated IBIS model generations for 65nm/90nm/0.13um image/graphic processing devices I/O macros for international customers, the turnaround time was only 2 days per device. Kilopass Technology (San Jose, CA) 2006 – 2009

Senior Staff Design Engineer

Team member of the OTP Memory Design. Develop analog circuits for sub-micron 0.18um/0.16um/0.13um/0.11um/90nm/65nm OTP memory IP designs, resolve unexampled circuit issues, research new circuit checks.

Built IP’s with Hspice/Hsim simulators and physical verification (DRC/LVS/ANT/ERC) with Calibre.

Renovated foundry vendor Calibre rule decks for OTP circuits for more detailed DRC/LVS reports and reducing debug time within 1 day (3 times faster).

Constructed low-power bandgap circuits and small foot-print high-voltage regulated charge pumps for technology nodes.

Created/documented 0.13um OTP patented programming algorithm, sense amp circuits, high-speed low-power sensing designs.

Verified system-level/transistor-level simulations using simulators, such as Spectre, Eldo, Hspice, Hsim, Ultrasim with respect to customer specifications.

Supervised/documented layout specifications to overseas layout teams.

Designed I/O circuits with above spec. ESD and high-voltage protected pad with analog OTP programming capabilities. ADDITIONAL RELEVANT EXPERIENCE

Neomagic Corporation, Senior Design Engineer / Team Leader Linkup Systems Inc., Senior Design Engineer

AnalogBit, Analog Design Engineer

Cyclonics, Senior Design Engineer

Chrontel Inc., Design Engineer/Supervisor-Test Engineering EDUCATION

Master of Science, Electrical Engineering

New York University, New York, NY

Bachelor of Science, Electrical Engineering

University of Southern California, Los Angeles, CA Associate of Science, Engineering (Honors)

City College of San Francisco, San Francisco, CA

MILITARY EXPERIENCE

US Air Force Reserve, Medical Group, Desert Storm Veteran MEMBERSHIPS and AFFILIATIONS

IEEE member

GARRY TSE ac0dmz@r.postjobfree.com ● 510-***-**** P A G E 4 PROPOSED PATENTS and PUBLICATIONS

Hierarchical Static Circuit Checks with Signal Integrity Analyses For Post-Layout Adaptive Programming Current Scheme For Generic CMOS Process OTP High Efficiency Ultra-high Voltage Charge Pump For OTP Programming Without Potential Oxide Breakdown After Programming Operation

High Speed Sensing Circuitry For Modified CAM Cell For Low Power Graphic Processing Cadence 2013 CDNLive:

The Hierarchical Approach For Full-chip Flash Memory Array Static ERC Synopsys 2013 SNUG:

Top-down Post Verification For SRAM Boundary Simulation with FinesimPro

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