Design Electrical Engineering

Gagandeep Singh

San Jose, CA ***** • 408-***-**** • *********.*******@*****.***

EDUCATION

SAN JOSE STATE UNIVERSITY, CALIFORNIA August 2015 – May 2017 M.S in Electrical Engineering GPA: 3.6/4

Related courses:

Advanced Digital System Design and Synthesis CMOS ASIC Design Advanced Computer Architecture SoC Design UVM verification with OOPs concepts Semiconductor Devices PUNJAB TECHNICAL UNIVERSITY, INDIA August 2010 - May 2014 B.Tech. in Electronics and Communication Engineering SKILLS

• RTL design, static timing analysis, DFT methods, logic simulation, design synthesis, and gate-level simulations.

• Verilog, System Verilog, VHDL, power and performance analysis, computer architecture, and CMOS VLSI design.

• SCAN, SoC bus protocols, SoC bus arbitration schemes, place and route, layout design, and floor planning.

• Design verification, test plan development, constrained-random test, coverage analysis, UVM, and assertions.

• Programing languages: SystemVerilog, UVM, C++; Scripting languages: Perl, Tcl, Python; OS: Linux, MAC OS X.

• Tools: Synopsys VCS, NC-Verilog, Design Compiler, PrimeTime, Cadence Virtuoso, Cadence Encounter, GTKWave.

• Excellent communication skills and strong team work spirit earned through projects and internship experience. PROJECT EXPERIENCE

RTL design and verification of AXI4-lite Protocol January 2017- May 2017 SystemVerilog, UVM, Synopsis URG SJSU, California

• A team of 2 Implemented AXI4-lite protocol which included Master and slave devices, used synthesizable system verilog constructs to successfully implement the protocol.

• Developed UVM class components, such as sequencer, monitor and driver, used constrained random testing and directive testing to check the code coverage and verify the design.

Implemented Network on Chip (NoC) September 2016- December 2016 SystemVerilog, Synopsis VCS, GTKwave SJSU, California

• Successfully implemented NoC bus architecture having various operation code. The NoC bus master logic using the NOC interface to fetch and store data to a memory in test-bench.

• Integrated CRC with NoC design to make CRC work as slave device and used “Bidding” arbitrator to select appropriate master to transfer data to slave.

Designed Bidding Bus Arbitrator November 2016 – December 2016 SystemVerilog, Synopsis VCS, GTKwave SJSU, California

• Implemented bidding bus arbitrator using synthesizable system verilog constructs.

• Bidding bus arbitrator was used to select proper master to send the data to slave and vice-versa, based on the sourceID and returnID respectively.

Implementation and Analysis of various 64-bit adders October 2016- December 2016 Verilog, Primetime, NC- Verilog, GTKwave SJSU, California

• Implemented RTL code in Verilog for 64-bit ripple carry adder, carry look ahead adder, and carry select adder with equal group size and different group size.

• Ran logic simulation, wrote Perl script to run synthesis using Design Complier, ran gate-level simulation, and performed static timing analysis using Primetime.

• Compared all adders in their timing, area, and power performances. Implemented Floating Point Multiplier (IEEE-754) February 2016 - March 2016 Verilog, Synopsis VCS SJSU, California

• Successfully designed, simulated and synthesized IEEE-754 floating point multiplier.

• Design was optimized to achieve 300MHz timing and pass gate level simulation. Designed 5-stage MIPS Processor October 2015 - December 2015 Verilog, Design Compiler, GTKwave SJSU, California

• Wrote RTL code for a single cycle, 5-stage pipelined MIPS processor tested by calculating dot product and factorial.

• Implemented the logic blocks of forwarding and stalling to avoid pipeline hazards. RTL Design and Verification of Router (Router 1x3) January 2015- March 2015 Verilog, Xilinx ISE, Questasim India

• Led the team to write Verilog RTL code for SoC router (1x3), consisting of FSM, synchronizer, register and FIFOs.

• Performed code coverage analysis, simulated the design, generated the waveforms to verify functionality.

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