Design Engineer Data
Resume:
Chih Kao (Jack) Hsieh
************@*****.***
www.linkedin.com/in/chihkao-jack-hsieh
Current address: Fremont, CA, 94555
Senior FPGA/ASIC Design/Verification Engineer
Technical skill
Technical experience:
1.Verilog/VHDL coding for high speed digital designs.
2.Build test bench for verification.
3.FPGA design with Altera, Xilinx FPGA.
4.FPGA prototyping.
5.Board design and bring up.
6.Ethernet Packet Traffic Manager, Packet De-queue Scheduler.
7.10G/1G Ethernet, SPI, I2C, RGMII, PCIe, DDR3, RLDRAM3.
8.Digital clock/data recovering design/verification.
9.System Verilog
10.Studied UVM.
EDATools:
1.Modelsim, NCSim, VCS, and Debussy.
2.Altera Quartus. Xilinx ISE/Vivado
3.FPGA Hardware Emulator (Veloce)
4.Design Compile, PrimeTime.
5.Synplify Premier for FPGA synthesis.
6.Logical Equivalence Check (Verplex and Formality).
7.Spirent Smartbits, Ixia Packet Generator/Analyzer tester.
8.Logic Scope, logic Analyzer.
Key Accomplishments:
1.Independent build Altera FPGA relate simulation test bench. Compare to signalTap debug method, this help to reduce product develop time.
2.Solve the legacy product issue. The customer using legacy product and having packet stop sending issue. I studied the issue and update the new MAC IP inside FPGA (Xilinx) to solve the problem. This help to keep the business with customer.
3.Came out new method for “Digital clock/data recovering”. This help the product running robust and packet transfer error free.
4.Patent. SONET TDM Data Byte Switch. http://www.google.com/patents/US20060155910
10/2013 ~ present IXIA Location: Santa Clara, CA
Principal FPGA Design Engineer
1.FPGA Design: Network Visibility Solution
●FPGA design (Altera Arria-10) for 16 ports 10Gig/1Gig Ethernet Visibility project:
-Functional specification, RTL coding, compile, board/FPGA bring up.
-Support interface including SPI, I2C, 10Gig Base-R/KR, Xaui, PCIe, DDR3, RLDRAM3.
●Build functional simulation test bench, using Verilog, System Verilog, Shell. TCL and Python scripts.
●Legacy product maintenance. 1Gig/10Gig IBYPASS products. Adding/Updating functions for customer requirements. Including Ethernet MAC IP update, ICMP header, support software team for FPGA relate issue.
4/2012 ~ 10/2013 Marvell Corporation Location: Santa Clara, CA
Staff ASIC Design Engineer
1.ASIC verification
●Using Formality/Verplex (LEC) to verify both RTL and pre-scan/post-scan/P&R Netlist. Checking the report file and find out if any issue.
2.ASIC Hardware Emulator and final release
●Setup Veloce (hardware emulator) system for ASIC functional validation.
●Running Veloce Emulator to verify both RTL and Netlist for final release.
7/2008 ~ 4/2012, Teknovus (Acquired by Broadcom) Location: Petaluma, CA
Principal ASIC/FPGA Design Engineer
1.ASIC/FPGA design/verification: EPON 1G/2G.
●Architecture and RTL coding: Increasing original EPON chip data path bandwidth from 1Gig to 2.5Gig.
●FPGA (Vertex-5) prototyping: Synthesis, placement and route, timing closure and lab bring up. The core clock is running at high speed 125/312 MHz.
2.ASIC/FPGA design/verification: EPON 10G.
●RTL coding for packet between Mac and “Smii, Mii, Rgmii” interface.
●Build test bench for Xaui, Xpcs module verification, also including code review.
●FPGA (Vertex-5) prototyping: The core clock rate is running at 312/250/125 MHz. Using high speed RTL design method, constrain file and PlanAhead to achieve high speed timing requirement.
●Synopsys Design Compiler for ASIC (40nm) power, area (including memory) estimation.
5/2000 ~ 7/2008, Cisco Systems Location: Petaluma, CA
Senior ASIC/FPGA Engineer
1.FPGA design/verification: Packet queue Management and De-queue Scheduler,
●RTL design/verification for Queue Management module (with Queue link list method). Packet store/forward via external RLDRAM2 and total 176 queues. The packet bandwidth up to 20Gbps.
●Independent design De-Queue scheduler module with MDRR (Modified Deficit Round Robin) method, including rate shaper, core clock rate is 175MHz.
●FPGA lab bring up: debug with Xilinx Chipscope and IXIA/SmartBit tester.
2.ASIC design/verification: Backplane Interface.
●Independent RTL coding for backplane Data/clock recovering (CDR) ASIC (0.18u)
●Come out new design method for recovering 311MHz clock from Data Bus (8 bit). This new method could help catch the reliable data bus signals from backplane.
3.ASIC verification: STS/SDH, VT level Cross connect ASIC
●32 by 32 Channel (OC-48C), SONET STS/SDH level Cross connect ASIC
Verilog and Synopsis Telcom workbench create test bench.
NCSim/VCS/Debussy run functional and gate level simulation.
Run formal equivalent checker to verify functionality between RTL and netlist file with.
●Come out new design method (patented) that can save RAM size on complex Cross connect ASIC.
1/1996 ~ 4/2000, Abatis Systems (Acquired by Redback) Location: Burnaby, Canada
Board/Hardware design Engineer
1.Board design/verification: Voice service Card
●Complete design/verification Voice service Card. The card include host processor, SRAM and 12 DSP, that provide voice packet transmit/receive between two T1 interface and PCI bus.
2.FPGA design/verification: Voice service Card
●Independent Complete design/verification by using FPGA (Altera Flex10k) to provide 48 DS0 Channels, which are routing between two T1 Framers and twelve DSPs.
●Complete design/verification by using CPLD (Altera 7000s) to provide data/address bus control among the MIPs, Memory and 12 TI DSPs.
3.FPGA design/verification: Data/Voice/Graphic Card
●FPGA (Xilinx XC4010E) for LAN Hub controller
Complete VHDL RTL design/verification to provided 12-port data detection and arbitration, and also provided FIFOs for data storage and data repeaters.
Patent
SONET TDM Data Byte Switch.
http://www.google.com/patents/US20060155910http://www.google.com/patents/US20060155910
http://www.google.com/patents/US20060155910
Education
Bachelor of Electrical Engineering.
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