Jacksonville, OR 97530
Cell - 541-***-**** firstname.lastname@example.org
Hardware description languages: VHDL, Verilog, Abel, CPL, Warp, and Palasm
Schematic entry programs: Orcad, Viewlogic, Dx_Designer, and Cadence
Simulators: Modelsim, Viewlogic, and Isim
Synthesizers: Synplicity, Xilinx XST, and Lattice Precision
Programming languages: perl, assembly, microcode, and C
FPGAs: Xilinx, Altera, Lattice, and Actel
Interfaces: VME, PCI, PCI-e,UART, I2C,SPI, MIPI, Camera_Link, SERDES, Ethernet,DDR
Since 1989 all designs have been FPGA-based and simulated. FPGA design includes synthesis, static timing analysis
And constraint creation. FPGA coding is in VHDL except where otherwise noted.
BSEE -- San Jose State, San Jose, CA
35+ graduate credits (Electrical Engineering/Hardware Design) -- UCLA, Los Angeles, CA
Designing low noise 16 bit Raman spectrometer for use in natural gas exploration
Utilized Spartan3AN non-volatile FPGA for image sensor control and image processing.
Design included automatic baseline control of image, low noise sigma delta image capture of image, various filtering techniques for displaying the image and multiple TEC controllers.
Zeiss Meditech, Dublin, CA 2/13 – 10/14
Image processing in hardware to prevent the laser in a laser driven eye examination system from burning the eye of the patient.
The design was FPGA based (non-volatile Spartan 3an) and included acquiring the reflected image from a laser x,y galvo deflection system.
System included serval FPGAs and high speed static rams and the FPGA code was written in VHDL.
Pinebrook, Santa Clara, CA 7/12 – 2/13
Camera design using 3 color 1kx1k Foveon CMOS sensor for use in a direct laser exposure PCB manufacturing system. Camera was used to monitor l the laser exposure of the PCB.
The camera design was FPGA based (Spartan 6) and the FPGA code was written in verilog
Fairchild Camera, Milpitas, CA 10/09 – 7/12
System design and hardware design of a low noise (16 bit) CMOS camera for scientific applications using a camera link interface.
The design is FPGA based (Spartan 6) and includes bad pixel correction, offset and gain corrections/pixel, hi and lo gain blending, binning, 16 possible ROI and an embedded microblaze processor for handling auto focus, light levels and general control functions.
The design also included a high speed internal block transfer bus for image processing, a camera link interface and a PWM controller for a peltier TEC that was maintained at a camera temperature of +/- .05C.
Designed color 16k pixel aerial surveillance camera using 2 concatenated 6 inch line scan sensors. Altera FPGAs (StraTix and Cyclone) used to control line scan sensors and to seamlessly abut the pixels of the two sensors.
Camera interfaced to compute through proprietary PCB.
Gatan, Pleasanton, CA 12/07 – 03/09
System design and hardware design of a low noise (16 bit) CCD camera for electron microscopes.
Performed both analog and digital design.
The design was FPGA based (virtex 5) and included horizontal overscanning, vertical overscanning, and digital CDS for increasing the number of effective bits.
The design also included a DSO (digitals sampling oscilloscope) in the FPGA to allow tuning of the CCD drive signals while the camera was cooled and in a vacuum.
All CCD timing was programmable by use of memory mapped execution tables that resided in the FPGA.
The FPGA controlled all CCD clocking signals to a Resolution of 75 pico seconds.
All of the advanced features of the Vertex5 were used in this design.
A customized Serdes interface transferred the image from the camera
Lightfleet, Camas, WA 8/06-10/07
System design and hardware design of a super-computer using a novel all to all interconnection scheme.
FPGA designs for direct high speed switching (10 Gbs) between any source computer blade and possibly multiple destination computer blades.
Implemented Lattice FPGAs in both Verilog and VHDL. Lattice was used because it offers a large number of high speed serial ports.
Grass Valley, Beaverton, OR 10/05-7/06
Hardware design of a video compression/decompression server for driving projectors for the movie industry.
FPGA design done in Verilog. Schematic entered in Cadence.
Liposonix, Bothell, WA 7/05-9/05
Consulting Hardware Engineer
Designed vga/dvi display system and process control for medical therapy instrument.
FPGA done in VHDL, modelsim and Xilinx XST synthesizer.
Infact-Data, Beaverton, OR 12/03-7/04
Consulting Hardware Engineer/FPGA Designer
System and hardware design of a USB-based 48-channel industrial monitoring unit which had a unique command structure whereby any channel (under program control) could control the operation of any other channel.
Design included a DSP, large Xilinx FPGAs and analog design.
FPGA done in VHDL, modelsim and Xilinx XST synthesizer.
Engineering Design Team, Beaverton, OR 7/01-12/03
System and hardware design of PCI-based image processing system.
Designed high speed 1k x 1k camera as front end for FPGA-controlled system.
ASCII commands controlled the camera operation. FPGAs done in VHDL, modelsim and synplicity.
SRC Vision, Medford, OR 1994-6/01
System and hardware design of entire PCI-based color image processing system in which various items on a conveyor belt were sorted on the basis of color and/or shape. Items included wood chips, tobacco and produce.
Pipelined design that included linear CCD cameras, camera controllers, frame buffers, normalization, LUT thresholding, hardware implementation of image processing algorithms, DSP hardware and air valve controllers that ejected specified items from belt.
Design incorporated linear CCD imaging arrays, large Xilinix FPGAs, large VRAMs, large DRAMs, DSPs. Customized PCI interface implemented in a Xilinx FPGA.
ASI, Salem, OR 1993-1994
System design, hardware design, and programming of microcontroller-based auto security system and associated microcontroller-based programming units.
IIMorrow/United Parcel Service, Salem, OR 1989-1993
System design, hardware design and debugging of the following:
A high speed (100 in/sec) label reader that used DSP, FFT and correlation ICs interconnected by large Altera FPGAs along with standard PALs. Input was 4096 pixel linear CCD. This label is currently on all UPS boxes and is distinguished by a bulls-eye surrounded by dots.
An 8 channel communications controller for a VME bus system. Used large Altera PLDs and an 8051 controller. Wrote the assembly language code for the 8051.
Redundant 486-based CPUs for VME bus system using TI PC chip set and large Xilinx PLDs for glue logic.