Rajveer Singh Lalawat

Electronics City, Phase-* Bangalore, Karnataka, India Pin-560100

Æ +91-913******* Q adbl8j@r.postjobfree.com

AREA OF INTEREST: Memory And Layout Design, Digital Circuit Design, RTL Design and Verification

Education

Academic Qualifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Indian Institute of Information Technology Gwalior, Madhya Pradesh M.Tech, VLSI DESIGN 2017–2019

CGPA:6.63

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Govt. Indira Gandhi Engineering College,Sagar Sagar,Madhya Pradesh B.Tech, Electronics & Communication 2009–2013

66%

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Miss Hill School Gwalior Madhya Pradesh

Intermediate, PCM,English,Hindi 2007–2008

68.72%

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Regional Convent School Gwalior, Madhya Pradesh

Matric 2006

79.00%

Notable Projects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ Mtech Thesis Design a ’Low Power High speed Single Ended Read Decouple SRAM Array’ A circuit design and simulations of SRAM Array is done in SCL-32nm technology node using H-spice tool by synopsys.schematic and Layout of the SRAM cell is design and generated using Cadence virtuoso(schematics and layout) and DRC and LVS is verified using cadence (Assura)and simulation is done using Cadence spectre

+ Mixed Analog & Digital Design Course project: Completed the following project of RF design at ABV-IIITM which is given by SMDP (Ministry of Communication and Information Technology, GOI).”Design of Register File (136 word X 32 bit) for Leon3 Processor’(February-April, 2018)’

A 136 word X 32 bit RF file is designed on SCL 180nm technology node using EDA tool Cadence Virtuoso and simulations are performed using cadence spectre in Centos environment. I am responsible for designing Bitline part and also coordinating with the design team of other modules of the RF and look over the integration part of each sub-module to ensure that the overall specifications of the RF being designed are achieved.Layout of the complete RF is also designed, DRC and LVS is verified using Calibre by mentor graphics

+ Academic Course : CAD For VLSI,Mixed Analog And Digital Design,Advance Operating system,Data Structure,Computer Architecture

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Technical and Personal skills

+ Technical Skills: CMOS Digital and Analog circuit design,Digital circuit design.

+ Industry Software Skills: Cadence Virtuoso (Layout and Schematic editor),Spectre,Assura, Calibre,Innovus,Xillinx-Vivado,modelsim,questasim.

+ Programming Skills: Verilog,System verilog,C,CPP,perl & Basic Idea of Python

+ Personal Skills: Quick learner, Good problem solving skill, Leadership,Co-operative and Adaptive nature, Determined to learn with practical approach Internship(RTL Design And Verification )

+ Organization:Sion Semiconductor Pvt. Limited, Bangalore(india)

+ Key Result Areas:

+ Work with micro architecture to develop specification for devices.

+ Uses of EDA tools,including simulation and synthesis perform through RTL coding(verilog).

+ Design a Real time clock using verilog.

+ Design a Traffic light control using verilog.

+ Work on serial peripheral interface(SPI)is a synchronous used for short-distance communicate using verilog.

+ Recently just work on the UART,it is a device that has the capability to both receive and transmit serial data.

Apprentice Engineer (Electronics Process Control department)

+ Organization:J.K.Tyre & Industries Limited, Banmore (MP)

+ Key Result Areas:

+ Input Output Testing, Field Instruments (RTD, Thermocouple, Pressure gauge, Level Switch, SMART Pressure and Temperature Transmitter, Pressure Switch. Interests and extra-curricular activity

+ Listening music

+ Playing cricket

+ Travelling

+ Photography

Achievements

+ Qualified GATE 2017

+ Rank 1, ABVIIITM, Gwalior for ‘Robowar-Mini’ in 2012.

+ Rank 1, IPS, Gwalior for ‘Robo Race’ in 2012.

+ Organizer and Coordinator of the Annual Techno-Cultural Fest. ‘Formula’ of ABV-IIITM in 2019. 2/3

Declaration

I hereby declare that all the information mentioned above is true and correct to the best of my knowledge.

Date:

Place: (Signature)

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