Design Engineer Performance Improvement

Ananth Chellappa

Ph: 404-***-****

******.**@*****.***

github.com/ananthchellappa

Summary IIT-educated analog designer with 20 years industry experience and eight sole- inventor patents. Consulted by peers for bandgaps, amplifiers, noise, mismatch, root-cause analysis, Cadence tips and top-level simulations. Strong analytical skills; good at scripting, simplifying and shrinking circuits, following through and driving issues to closure; fast learner, initiative-taker, relentless self- improver, organized and time-sensitive person with a broken-windows mindset. Power user of Cadence, perl and Excel.

Key Contributions

● Responsible for three generations of TX Controllers in Qorvo’s RF module, achieving significant performance improvement and shrink in bandgap refs and temperature sensors

● Designer of on-chip LDO for AMD’s next-generation (Rembrandt) processor – up to 6A

● MAX77387 : Industry’s smallest 2A boost solution (2011). Full ownership of the peak- current-mode boost (reuse of topology and blocks with substantial changes); Team of 4 delivered white-LED driver. Maxim’s first dual-phase boost regulator.

● MAX8989 : Hysteretic buck PA supply – schedule critical (2009) – minor changes to core. With customer-requested derivatives, over 200 million units through 2012. One person team.

● PTN5100 (NXP USB-Type-C Power Delivery IC, 2014) - Complete ownership of power- subsystem

● TI Scanner AFE (2007) : New, fully-isolated bandgap and reference section and work on pipeline ADC gain-stage amp. 100% market share for TI at HP for first year.

● TI Touchscreen AFE (2008) : Design of new TIA with reduced IQQ and improved noise; debug of issues gating production of 1

st

generation part designed into 3GS iPhone.

● 700+ lifetime tickets with Cadence to address bugs and missing features in Cadence schematic entry GUI and spectre/AMS simulators. Several features added to MG Tanner Tools S-Edit based on my feedback

● Approximately 100 mini projects completed through freelancers on Upwork to build productivity-boosting utilities in python, perl and Excel-VBA – almost all freely available on my GitHub page

Work Experience

Qorvo Staff Design Engineer

Chandler, AZ Mar 2022 – Dec 2024

● Supervised summer intern to take him from zero experience to being productive in basic design and optimizing analog circuits for area and variation using statistical simulations and advanced simulation techniques such as trim-and-sim with ADE- Assembler.

● Drove adoption of UMC Gen4 55 nm SOI within group by designing bandgap and temperature-sensor on my own initiative, which later turned out to be crucial in meeting a big customer sample schedule. New PA Bias IDAC 2.5x smaller than legacy ported solution. TX Controller (an IC providing bias to the PAs and antenna-selection module) shrunk 20%

● Re-designed RF PA-input-power-level detector (5-15 dBm threshold, programmable) on tight schedule to eliminate variation (0.7 dBm std-dev 0.3 dBm) and found cause of large variation of existing IP.

● Re-designed temperature sensor in GF SOI process to achieve 65% shrink. Used Monte-Carlo analysis to identify contributors to allocate area accordingly. Eliminated its dedicated 0.7V bandgap and redesigned main-bandgap to deliver necessary performance in -35 to 130 C range. Comparator redesigned for 3x lower delay with 6x lower IDD. Re-designed voltage-reference for PA bias DAC to be 65% smaller with overshoot completely eliminated and spread in voltage reduced 2.5x.

● TX Controller IC for a smartphone RF module – analog lead of a two person team

(analog + digital). 100% reuse of blocks. On-time tapeout. Complete ownership of top-level schematic, verification. This was for the diversity-switch-module (DSM). On my own initiative, I redesigned the charge-pump on the PA+Diplexer module to have less noise using a higher clock and interleaving to give a night/day difference per the system-engineer in linearity measures (QAM, etc)

● Buck-boost switching regulator for 5G PA : full ownership of reference (BG reused, other blocks from scratch) and voltage-control (error-amp) section (no issues on silicon) and top-level schematic. Follow on part to QM81050.

● TX Controller IC for smartphone RF module (containing PA, LNA, CTRL and Antenna SW) – owned re-used blocks such as LDOs and PA bias-generator. Drove hookup of top-level of the analog section. First-pass silicon with minor bugs.

● Three disclosures, one patent filed. Two invited presentations to company-wide audiences - best practices for basic design - current-mirrors, etc and productivity tips. Several EDA/CAD contributions related to PDK usability/UX to boost productivity of layout designers. Also learnt use of Virtuoso auto-router to be able to do layout of blocks to help schedule. On UMC Gen4 project, helped layout team by using autorouter to do 200+ top-level digital routes.

NuVolta Technologies Senior Analog Design Engineer Remote Dec 2020 – Mar 2022

● Analog design for Battery Management Gas Gauge IC : new 1% (post-trim) relaxation oscillator with 1.5 uA max IDD (65 kHz). First-pass working silicon.

● Lead analog designer for protocol IC (big Digital) to allow Smartphone OEMs to support VOOC/UFCS/BC1p2/etc. Complete ownership of all analog and top-level verification. Designed LDO using fast (Bazes) comparator to improve load-transient response.

● Wireless Charging TX IC : two high-voltage (30VIN) current-sense circuits for a buck-boost and H-bridge using BJTs to minimize random offset.

● 5A LDO for a 100W wireless charging RX (Previous gen supported 2.5A and had stability issues with current-limit) – functional silicon with no reported issues.

● Designed sub 1 uA bandgap in TSMC 0.18 um (existing IP ~ 15 uA) for battery charger for wireless earbuds and supported top-level simulations. Created templates for design reviews docs and top-level simulation reports to improve methodology and productivity.

Vidatronic Senior Analog Design Engineer

Austin, TX June 2018 – Sept 2020

● Designed a new 140 mA buck regulator in TSMC 40 nm from scratch (architecture derived from seven-year-old predecessor IP in 110 nm). All blocks designed from scratch and additional features (SKIP mode, ramp compensation for stability at high duty-cycle)/range achieved. VIN up to 4.2V. Vo 1V/1.85V, IQQ ~100 uA. Mentored junior designers on individual block designs such as the power-stage and on-chip LDOs and concepts such as mismatch. Routines developed in perl/shell/python to process corner simulation outputs to generate Excel reports for documentation and identification of worst-case SOA violations. Drove Cadence to provide Exceed on Demand and also drove adoption of JIRA for issue-tracking.

● Contractor on AMD site supporting power-management portion of large SoCs - high current (5+A) high-bandwidth LDOs. Designed newest 7 nm chip-LDO supporting 40% higher load-current than existing IP with support for over-clocking (high voltage support). Designed output-voltage detect module from scratch. Worked on the Cache LDO current-sharing control for the Mero program - ensures the two LDOs feeding the cache have load within 15% of each other. Several perl/python/shell scripts developed to boost productivity considerably. Influenced AMD CAD policy wrt simulation license usage, and inspired enhancements to some internal AMD tools. Owner of the team’s CAD-how-to database aimed at rapid on-boarding and adoption of best practices.

Silanna Semiconductor Senior Analog Design Engineer Raleigh, NC May 2016 – May 2018

● Lead designer for metal-spin of general-purpose buck-regulator controller+gate-driver IC, targeted at USB-PD charger market. Owner of top-level and key blocks (Current- sense, LDOs, etc) . Drove RCA and fix of the bimodal operation issue preventing operation at low duty cycles. Expected to tapeout end 5/2018.

● Lead designer for ESD test-chip aimed at generating data for optimal 5V and 30V ESD cells. Responsible for about 30 die variants on the MPW.

● Drove top-level verification of controller-IC by setting up mixed-mode simulations accompanied by documentation to onboard new team members to contribute productively. Several structural and veriloga behavioral models created to speed up top- level simulations. Also drove use of bug-tracking utility to report/resolve issues. Created templates for design reviews and simulation result capture based on the best-practices of Maxim, NXP and TI. Requested to travel to HQ by PTE team to help first-silicon debug and requested to extend stay to help with test-development.

● Designed several modules for first controller-IC product and owned top-level hookup completely. Configuration resistor decoder (RCONFIG) - enhanced existing IP from 4- bit to 5-bit while reducing area. Redesigned temperature-sensor to reduce area 60%. SAR 10bit ADC - took ownership, fixed bugs and made minor tweaks to reduce offset. Designed self-test module for ADC from scratch. Re-designed error-amp to reduce gain and offset spread with acceptable INCM tradeoff.

● Test-mode input-buffer design and UVLO circuit design on tight schedule for gate- driver chip (working silicon)

● Empowered apps team through analysis and documentation of core blocks and architecture of controller test-chip; presented controller architecture to global design team; identified workaround to be used with foundry PDK to boost layout team productivity. Created utility within Cadence to help co-worker rapidly browse floating nodes reported by simulation to waive false reports. Responsible for over 90% of help- documents aimed at tool/productivity/best-practice knowledge sharing to quickly ramp up co-workers (schematic guidelines, AMS sims, Magwel how-to, etc) Recognized throughout company for productivity and quality of technical documentation in enabling teammates.

Sensor Creations Analog Design and Layout Engineer Camarillo, CA Mar 2015 – Apr 2016

● Circuit design, layout and scripting for scientific-grade CMOS image sensors; mentoring of 3 junior engineers.

● Design: 14b (3 sigma DNL 8 LSB) 500 KSPS multiple-slope ADC with 10 micron pitch in 0.18 um CMOS – significant revision and new additions to 3 year old design which was non-functional. Circuits for data handoff at DDR with 200 MHz clock, over LVDS. Functional silicon requiring moderate re-work to enter production in military application.

● New vertical and horizontal scanners supporting arbitrary regions of interest, binning and bi-directionality for next generation HDTV resolution thermal imaging ROIC. Lead designer for 100 fps imager for genome-sequencing application: re-designed 25 MSPS output-buffer and line-driver to have 50% lower power consumption and improved accuracy (3.3V). Drove signal-chain analysis to arrive at circuit-level decisions for 5e- noise performance and designed AFE amplifier for pixel interface. Drove adoption of veriloga for order-of-magnitude boost in verification productivity.

● Layout : layout of 15 micron pixel with added functionality. Introduced concept of integrated well ties; scripting for easy location of DRC errors for an order-of- magnitude boost in productivity. Also drove adoption of Schematic-Driven Layout in Tanner tool-suite (equivalent of Cadence XL) to boost productivity – required adoption of new PDK, which in turn required scripting for design migration, to yield significant boost in layout productivity.

● Initiative : Several utilities in TCL to boost productivity in the Tanner environment. Introduced HDL-coding+synthesis based digital design using open source tools for quicker and more maintainable digital design and created a verilog import utility (perl

+ TCL) to generate schematics in Tanner from gate-level verilog netlists. Over 100 bug reports and feature requests on Tanner EDA to close the gap with Cadence. Pursued relationships with EDA vendors to drive tool purchase designs by demonstrating value with evaluation licenses.

NXP Semiconductors Senior Analog Designer

Phoenix, AZ Aug 2013 – Dec 2014

● Recruited to design circuits for the USB-Power-Delivery product line.

● PTN5100 (2

nd

in line, 2H14) : : Owner of power-subsystem and bias. Simplified and shrank circuits for more aggressive die-size and IQQ reduction, further 50% reduction in IQQ in SYS-pwr detection over PTN5001. Added soft-start current-limiting on own initiative. Functioning as expected on silicon.

● PTN5001 (1st product in line) : Designed relaxation-oscillator (reuse) based FSK- modulator (from scratch). Improvements to oscillator fed back to IP source. Full ownership of central bias (minor mods), clock-generator for digital-core (minor mods), cable-detection module (from scratch), dig-ana isolation cell (from scratch), power-FET drivers (reuse, minor-mods), system-power detection (50% IQQ reduction over original IP), supply-rail status-monitors (from scratch). All blocks functioned as expected on silicon. Best-in-class demo at InterOp trade-show.

● Pipeline : Redesigned TX-line-driver of PTN5001 achieves 70% IQQ reduction and 85% area reduction. Proof-of-concepts (some implemented in PTN5100) for 70% area reduction of power-subsystem of PTN5001. Ideas for 80% area reduction in Over- current protection circuit of PTN5001.

● Other product lines : Convinced NFC-Boost team to adopt a certain control scheme based on my experience and required min duty-cycle. Team also later adopted my suggestions for current-sensing and PWM comparator implementation styles.

● Initiative : Owned and upgraded analog guidelines doc, primary liaison with Solido, did layout of 10+ blocks on PTN5100 to help schedule, full validation of verilog behavioral models of power-subsystem of PTN5100 to help verification team.

● Mentorship : coached other designers on mismatch, PSRR, NBTI, veriloga, debugging and cadence-productivity (bindkeys, sensitivity-analysis).

● Patents : Modified Dickson charge-pump, low-VDD bandgap buffer, low-power regulator, low VDD IREF, compact PTAT cell all (4) granted by USPTO Maxim Integrated Products Member of Technical Staff, IC Design Phoenix, AZ July 2009 –Aug 2013

● Miscellaneous contributions on multiple projects : (most recent) buck-regulator IP for a critical project with an important customer - found ways to shrink die-size through optimal use of process and architectural changes. Shrank clock-generator block more than 50% by redesign; shrank digital-comparator and counter used in slew-rate controller 40% each by following an HDL+synthesis approach to replace the hand- designed legacy IP. Owner of reference section; reduced process-variation in soft- start slew-rate by moving to new topology.

● New battery-charger I/P in Maxim’s 90 nm process : full ownership of the ADC section - reusing 14b ADC provided by the ADC group and designing custom REF buffer and input buffer (moved to buck-regulator project which was more critical)

● Four-phase 12A buck regulator - responsible for validation of testmodes and providing design-for-test documentation to test-team. Also played a key role in tracking down layout-parasitic issues. Achieved important milestone for the group by delivering a script that could be run to re-run all testmode simulations automatically to save effort on future passes. Also handled configurable clock-generator design for this multi- phase buck.

● First testchip in Maxim’s 90 nm process – power-stage section containing simple switch drivers – about 25% of a 8x8 pin array chip - error-free silicon; follow-on device to the MAX8989 – design tweaks driven by customer needs to retain vital socket at top-tier customer; termination-supply for low-power DDR interface on e- Reader PMIC; MAX77693 – PMIC used in Galaxy 3 handset – safeout LDOs – design tweaks and top-level hookup; verification of flash-LED driver;

● Design of Maxim’s first dual-phase boost-regulator in a flash-LED driver application (MAX77387 : 2A max load, 5.5Vo max). Adapted single-phase current- mode architecture with required modifications. Design activity influenced all blocks. Reduced PWM comparator delay about 4 ns (from 20 ns) through minor design change and optimized layout. Extensive parasitic back-annotation done to ensure good current-balance between phases, and extensive design-reviews conducted to ensure first-pass success with only minor issues. Also owned top-level bias-generator and drove top-level simulation methodology. (4 person team, 2011)

● Support on flash-LED driver section of PMIC device – top-level simulations, parasitic-extraction to identify root-cause of issue on first-pass

● Design lead for a cellphone PA 9-pin 2.5A power supply device (MAX8989). Taped out the design with an aggressive schedule. Oversaw addition of new functionality to support PROM readback. Reused core IP and added testmodes to support datasheet. First-pass silicon fully functional, issues resolved with EVK redesign. Currently shipping in high volume.

● Took over responsibilities on a new power supply device; responsible for driving electrical correlation of production tests and miscellaneous milestones to release to production. Introduced new top-level simulation methodology to group. Designed a new PC-based interface (PC GUI, MCU software and custom PCB all from scratch) to communicate with the chip in testmode to improve on the status quo hardware of a board with push-buttons and no visual feedback. Took the initiative to convert this design database from an outmoded design-platform to Cadence – which later permitted two projects using the IP to be executed with aggressive schedules.

● Enhanced group productivity by introducing new methodology for doing mixed-signal top-level simulations using verilog pattern generators instead of PWL voltage waveforms to handle I2C and SPI comm, and fanning out time-saving shortcuts in the cadence suite. Mentored other designers on statistical simulations in the cadence environment. Nominated as group advocate to fanout a new corner simulation tool. Conceived, prototyped and worked with EDA group to create a new tool to assist designers in back-annotating floating nodes. Several presentations by invitation. Texas Instruments Analog Designer

Dallas, TX Oct. 2005 – Apr 2009

● Capacitive-touchscreen AFE chip (90 nm). Designed receiver frontend amplifier to achieve new spec (linearity/bandwidth/noise) with same power and comparable area. Other accomplishments were design and improvement of miscellaneous amplifiers in the RX chain, redesign of LDOs based on silicon eval of previous version. Drove root- cause analysis of four issues observed on device – hi-temp LDO failure, LDO transient issue, 0.2% powerup fail-rate in field and statistical yield loss in RX-SNR. Identified several improvements to be implemented in current chip. (from 2H 2008)

● Various tasks on notebook battery charger PMIC for Apple Inc. System Oscillator

(reduced area ~50%), verification of misc. blocks, macro-modeling of blocks for top- level simulation, top-level sims. Recruited to help meet schedule. (2Q 2008)

● Complete ownership of 3 buck DC-DCs for PMIC for portable GPS product. (reuse, minor mods, 1.8-6.5V Vin, 0.7-3.3V Vout, 2A max load) Drove top-level tasks (drove pkg modeling, testmux, top-level simulation setup) to help project schedule. Also designed thermal shutdown ckt (from scratch). Developed critical workaround to trim system-oscillator when primary method was not available. (2-4Q ‘07)

● Buck-boost regulator for DSC PMIC (reuse, minor mods, 1.8-6.5V Vin, 3.3V Vout, 600 mA load) Identified root-cause of wide variation of current-limit as random-offset of i-sense amp (1Q 07)

● Scanner AFE: Full ownership of reference system (bandgap, pipeline ADC differential reference – new fully-isolated bandgap topology; all blocks from scratch – led to 3 patent filings). Design of pipeline ADC residue amp. Helped define ADC architecture. Lab debug of first silicon. (2H 2006)

● Portable laser projection display PMIC: Complete ownership of reference system. New current reference topology. All blocks from scratch – low-noise bandgap, low- noise linear regulators, internal buffers. Autozero amplifier for use in laser temperature-stabilization loop (from scratch, reusing topology, <50 uVVos). Complete ownership: Supply monitor circuit. Input buffer, testmux, Also did EEPROM hookup and layout of i-ref block. (1H 06)

● Mentored other designers on bandgaps, LDOs, statistical simulations for mismatch.. Patent filings are in the areas of bandgap-reference, temp sensor, bias-generation and POR circuits. Conceived and outsourced development of a tool to locate spare devices in a design.

Analog Devices Inc. Design Intern

Tucson, AZ. Jan. 2005 – July 2005

Design of a low-power high-precision op-amp in a 0.6 um process: Rail-to-rail input and output stages, temperature independent current reference, oscillator, clock generator, PLL based clock-multiplier (Maneatis scheme).

Georgia Institute of Technology Graduate Research Assistant Atlanta, GA. July 2001 – Jan 2005

High-speed analog design with the goal of an inductorless 10 Gbps optoelectronic RX in a 0.18 um CMOS process. Individually designed, laid out, fab’d (MOSIS 0.5 um) a chip with 400 MBPS chip and demonstrated it in the lab. Used BERTs and network analyzers. Texas Instruments (India) IC Design Engineer

Bangalore, India July 1998 – March 2001

● Designed two PLL's per the self-biased scheme of Maneatis (JSSC, Nov1996 ) for a flat panel timing controller ( TFP74x3 family). Loop filter design and modeling and simulations of all blocks of the PLL. User defined modules created for certain blocks to reduce simulation time with TISPICE simulator. Also modeled a PLL in VHDL to investigate effect of spread-spectrum clocking for EMI reduction

● Developed DAC and Switched Cap. Filter for a 16 bit 26 KSPS Sigma Delta Analog interface circuit in a 0.35 um process. First S-D DAC channel to achieve over 90 dB THD. Was since reused in two more products. Worked on an 8 ohm speaker driver in a 0.5 micron process on same project

● Designed a 14 bit recyclic ADC in a 0.6 micron process ( at the block level reusing amplifiers and comparators )

● Analog design of an 8 bit resistor string DAC for a Digital Still Camera Analog Front End (AFE) and Modeling in VHDL of entire AFE and Design, synthesis and autolayout of control logic for a 14 bit pipelined ADC of the same AFE.

● VHDL digital design of control for a current steering DAC and SAR ADC Education

Georgia Institute of Technology MS in ECE: 2003, GPA 3.87 Indian Inst. of Tech.(IIT), Madras, India B. of Tech. in Electrical Engg. GPA : 8.26/10 Patents

9906127 NXP Fractional output voltage multiplier

9817426 NXP Low quiescent current voltage regulator with high load-current capability 9753471 NXP Voltage regulator with transfer function based on variable pole-frequency 9519298 NXP Multi-junction semiconductor circuit and method 7920015 TI Methods and apparatus to sense a PTAT reference in a fully isolated NPN-based bandgap reference

7843254 TI Methods and apparatus to produce fully isolated NPN-based bandgap reference

7821307 TI Bandgap referenced power on reset (POR) circuit with improved area and power performance

7780346 TI Methods and apparatus for a fully isolated NPN based temperature detector

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