| Resume alert | Resumes 71 - 80 of 128 |
Electrical Engineer Design
Pasadena, CA
... encoders & compressors Designed filters for sensor, video (NTSC & FireWire) and RF input data interfaces Customized VHDL/Verilog FPGA code to utilize Opal Kelly board as a RS422 to USB converter with DDR2 buffers and CCSDS packet/ frame interpreter ... - 2013 Oct 29
... encoders & compressors Designed filters for sensor, video (NTSC & FireWire) and RF input data interfaces Customized VHDL/Verilog FPGA code to utilize Opal Kelly board as a RS422 to USB converter with DDR2 buffers and CCSDS packet/ frame interpreter ... - 2013 Oct 29
Engineer Electrical Engineering
Los Angeles, CA, 91775
... Verilog HDL, Matlab COURSES RELEVANT COURSES Analog/Mixed-Signal Integrated Circuits (EE 536a/b), VLSI system design (EE 577a), (USC) Digital Signal Processing (EE483), (USC), Communication Principle, Solid State Physics, (NTU) PUBLICATION Hsieh, Y ... - 2013 Jun 25
... Verilog HDL, Matlab COURSES RELEVANT COURSES Analog/Mixed-Signal Integrated Circuits (EE 536a/b), VLSI system design (EE 577a), (USC) Digital Signal Processing (EE483), (USC), Communication Principle, Solid State Physics, (NTU) PUBLICATION Hsieh, Y ... - 2013 Jun 25
Electrical Project Engineer
San Gabriel, CA, 91775
... (PLC) Allen Bradley RSLogix, Mitsubishi PLC (MELSOFT GX Developer & GT Designer2), Siemens PLC Step 7-Micro/WIN, NC Verilog, Xilinx ISE, PIC C Complier, and WorkBench v5 (Balder PLC) Programming Languages Visual Basic, Java, Visual C++, and ... - 2013 Jun 14
... (PLC) Allen Bradley RSLogix, Mitsubishi PLC (MELSOFT GX Developer & GT Designer2), Siemens PLC Step 7-Micro/WIN, NC Verilog, Xilinx ISE, PIC C Complier, and WorkBench v5 (Balder PLC) Programming Languages Visual Basic, Java, Visual C++, and ... - 2013 Jun 14
Design Engineer
Los Angeles, CA, 90007
... Modified the RTL code of MPEG-2 transport stream (TS) data transmission over IP based networks design in Altera FPGA using Verilog HDL. . Rebuilt the original FPGA designs into new devices within different version of Quartus II including full ... - 2013 Apr 11
... Modified the RTL code of MPEG-2 transport stream (TS) data transmission over IP based networks design in Altera FPGA using Verilog HDL. . Rebuilt the original FPGA designs into new devices within different version of Quartus II including full ... - 2013 Apr 11
Engineer Engineering
Los Angeles, CA, 90063
... • Community Service through Kellogg Honors College Fall 2007-June 2011 o Help set up events, organize and give people directions • Hands-On Experience in Labs o Programming using C, C++, MATLAB, Verilog, and Assembly o Using a voltmeter, ohmmeter, ... - 2013 Mar 26
... • Community Service through Kellogg Honors College Fall 2007-June 2011 o Help set up events, organize and give people directions • Hands-On Experience in Labs o Programming using C, C++, MATLAB, Verilog, and Assembly o Using a voltmeter, ohmmeter, ... - 2013 Mar 26
Quality Assurance Project
Los Angeles, CA
... Language: C/ C++( Open CV, Open GL), Java, Matlab, XML(XSLT, XPath), SQL, Software: MS Office, Photoshop, Protel, Multisim, Verilog, ArcGIS Desktop, Anvil System: Windows(XP,Vista, Win7), Mac OSX, Unix, Linux Hardware: PCs, Mac Work Experience ICT ... - 2013 Feb 28
... Language: C/ C++( Open CV, Open GL), Java, Matlab, XML(XSLT, XPath), SQL, Software: MS Office, Photoshop, Protel, Multisim, Verilog, ArcGIS Desktop, Anvil System: Windows(XP,Vista, Win7), Mac OSX, Unix, Linux Hardware: PCs, Mac Work Experience ICT ... - 2013 Feb 28
Project Manager Design
Altadena, CA
... Computer skills Programming Languages Verilog Synthesizable for ASIC implementation and FPGA, timing closure; verification testbenches, post-place and route simulations... Matlab High-level system simulation; image processing algorithms validation ... - 2013 Feb 22
... Computer skills Programming Languages Verilog Synthesizable for ASIC implementation and FPGA, timing closure; verification testbenches, post-place and route simulations... Matlab High-level system simulation; image processing algorithms validation ... - 2013 Feb 22
Design Project
Los Angeles, CA
... 4) DDR2 Controller Design Tools used: NCSim, NC-Verilog, Synopsys DC FALL 2009 VerilogHDL design of DDR2 controller using Denali s 512Mb software model based on JEDEC specs and Synthesized in 0.18um technology using Synopsys DC. 5) 5 stage Pipelined ... - 2013 Feb 14
... 4) DDR2 Controller Design Tools used: NCSim, NC-Verilog, Synopsys DC FALL 2009 VerilogHDL design of DDR2 controller using Denali s 512Mb software model based on JEDEC specs and Synthesized in 0.18um technology using Synopsys DC. 5) 5 stage Pipelined ... - 2013 Feb 14
Signal Processing Engineering
Los Angeles, CA
... Simulation, Design and Testing Tools: VPIphotonics, Rsoft OptSim, LabVIEW, Verilog HDL, Altera s Quartus II, OrCAD/PSpice Programming Languages: C/C++, Matlab COLLABORATION EXPERIENCE Collaborated with groups at: Telcordia Technologies (Drs. ... - 2013 Feb 13
... Simulation, Design and Testing Tools: VPIphotonics, Rsoft OptSim, LabVIEW, Verilog HDL, Altera s Quartus II, OrCAD/PSpice Programming Languages: C/C++, Matlab COLLABORATION EXPERIENCE Collaborated with groups at: Telcordia Technologies (Drs. ... - 2013 Feb 13
Engineering Electrical
Los Angeles, CA
... Tools LLNL Chemical Safety Cadence IC design tools LLNL General Employee Radiological Training Mathcad Synopsys Tools Verilog & VHDL Origin C/C++ PC/Mac/Unix OTHER Oral and Written Communication Data Organization & Analysis Written Procedures ... - 2013 Jan 26
... Tools LLNL Chemical Safety Cadence IC design tools LLNL General Employee Radiological Training Mathcad Synopsys Tools Verilog & VHDL Origin C/C++ PC/Mac/Unix OTHER Oral and Written Communication Data Organization & Analysis Written Procedures ... - 2013 Jan 26