Design Engineer

HANG LI

Address: *** * **** ****** *** B, Los Angeles, CA, 90007 E-mail:

abq25x@r.postjobfree.com Cell: +1-213-***-****

OBJECTIVE

New college graduate seeking a full-time job or an internship in the

field of digital design and verification, FPGA design and physical design

U.S. INTERNSHIP EXPERIENCE

KTech Telecommunications, Inc. Los Angeles, USA

Electronics Design Engineer Intern 01/2013 - Present

. Modified the RTL code of MPEG-2 transport stream (TS) data

transmission over IP based networks design in Altera FPGA using

Verilog HDL.

. Rebuilt the original FPGA designs into new devices within different

version of Quartus II including full compilation and SignalTap II

Logic Analyzer debugging.

EDUCATION

University of Southern California (USC)

Los Angeles, USA

Master of Science, Electrical Engineering (VLSI), GPA 3.41/4.00

Expected Graduation 5/2013

Coursework: VLSI System RTL Design (EE577b), VLSI System Full-Custom

Design (EE577a), MOS VLSI Circuit Design (EE477), System Design Using X86

Microprocessors (EE454), Computer Systems Organization (EE457), Analysis

of Algorithms (CSCI570), Solid State Processing & Integrated Circuits

Laboratory (EE504), Parallel and Distributed Computing (EE657)

Tianjin University of Science & Technology (TUST) Tianjin, China

Bachelor of Science, Electrical Engineering & Automation, GPA 3.90/4.00

09/2007 - 07/2011

National Scholarship from Ministry of Education of China for the 1st rank

SKILLS

. Programming Languages: Verilog HDL, C, Perl, Tcl, Assembly Language

. Tools: Altera Quartus II, Cadence (Virtuoso, NC-Verilog, Layout,

Schematic, NCSim, DRC, LVS, P&R), Spectre, Modelsim, Synopsys,

Matlab, Keil, Proteus, Multism, Protel

ACADEMIC PROJECT EXPERIENCE

DDR2 SDRAM Memory Controller (Verilog coding, NCSim, Synopsys)

09/2012 - 11/2012

. Designed a RTL level DDR2 controller in Verilog HDL with Denali 512Mb

(32Mb x16 four bank) DDR2 model, synthesized the design using

Synopsys, achieved static timing analysis

Image Noise Attenuation (Full-Custom design, Virtuoso, Spectre, DRC, LVS)

03/2012 - 05/2012

. Designed the schematic of 1K (64*16bits) SRAM storage including

sizing to improve function, speed and power, and corresponding layout

implementation

. Implemented the logic design of uniform noise attenuation algorithm

of 8*8 pixels in hardware by consulting neighboring pixels of each

pixel

Five Stage Pipelined CPU (Verilog coding, Modelsim, NC-Verilog) 03/2012

- 04/2012

. Designed a five stage pipelined CPU under structural and RTL level,

programmed with Verilog HDL

Bi-Directional Digital Timer (Full-Custom design, Virtuoso, Spectre, DRC,

LVS) 10/2011 - 11/2011

. Designed the Schematic & layout of a count up/down digital timer

through one-hot coded state machine with Cadence Virtuoso, including

logic design, optimization of crosstalk, area and delay

Interfacing of memory and I/O to Intel x86 processors (Virtuoso,

Modelsim) 08/2011 - 12/2011

. Achieved Interfacing of processors including Intel parallel and

serial I/O chips 8255A & 8251A, interrupt controller 8259A, FIFO, DMA

controller 8237A, bus arbiter 8289, clock generator 8284 and

different data-bus width to a global memory via a shared bus

FPGA Based Frequency Spectrum Analyser (Verilog coding, Quartus II,

Modelsim) 01/2011 - 07/2011

. Achieved RTL design of Frequency Spectrum Analyser based on FPGA

including digital/analog convert, data buffering, Fast Fourier

Transform (FFT) and LCD display control

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