Engineer Electrical Engineering

Tu-I, Tsai

Email: abzh48@r.postjobfree.com, Phone: 626-***-****

OBJECTIVE

OBJECTIVE

Seeking Analog/Mixed-signal Layout engineer, Analog/Mixed-signal ASIC design engineer (start from

Analog/Mixed

ixed- engineer, Analog/Mixed

ixed-

2013 Dec.)

EDUCATION __

Los Angeles, CA

University of Southern California (USC)

Uni (USC) Sept./ 2011-Present

University

Doctor of Philosophy tracking student in Electrical Engineering, GPA 3.66

Masters of Science in Electrical Engineering (Expected Graduation Dec/2013)

Taipei, Taiwan

National Taiwan University (NTU) Sept./ 2006-June/ 2010

Bachelor of Science in Electrical Engineering, GPA 3.97/4.00, ranked 18/224 (top 8%)

RESEARCH EXPERIENCE

Tape-out 12bit, 1GS/s DAC with pure digital foreground calibration, (USC)

Tape-

Tape calibration, May/ 2013

Modeled and architected entire chip from algorithm development, transistor level design, to

post layout verification, tape-out in TSMC65nm.

Novel architecture enables high resolution/dynamic range (SFDR > 80dB, state-of-the-art:

70dB), GHz DAC application

Parallel/Pipelined high speed Delta Sigma Modulator (1GS/s, 8GS/s, 1-1-1 MASH)

Custom designed CML logic, phase rotator, bang-bang phase detector, clock divider at 8GHz

CLASS PROJECTS

10bit 20MHz 2nd order Delta Sigma ADC in 45nm technology, (USC)

10bit 20MHz order Sigma technology

ogy, May/ 2012

Matlab modeling of ADC and its stability criterion,

Designed switch capacitor opamp, performed system level debugging

ENOB: 8.5 bit, Bandwidth: 20MHz, FoM: 0.48pJ/conv

Digital Image Processor Implementation, (USC)

Implementation May/ 2012

SRAM design 1024 bits, Carry-Look-Ahead (CLA) Adder, Multiplexer, Digital Controller

Transimpedance Amplifier, (USC)

Amplifier, Sept / 2011

Three stage amplifier with feedback and supply independent biasing

Low-

Low-dropout (LDO) Voltage Regulator, (USC)

Regulator,

From schematic design to post layout verification (including Bandgap reference

reference) July/2013

TECHINICALSKILLS

Cadence Virtuoso (ADE, Layout, AMS) and Ocean scripting; Mentor Graphics Calibre

DRC/LVS/PEX, Synopsys Nanosim; Verilog HDL, Matlab

COURSES

RELEVANT COURSES

Analog/Mixed-Signal Integrated Circuits (EE 536a/b), VLSI system design (EE 577a), (USC)

Digital Signal Processing (EE483), (USC), Communication Principle, Solid State Physics, (NTU)

PUBLICATION

Hsieh, Y.S ; Wang, K.C. ; Chun-Ting Chou ; Hsu, T.Y. ; Tsai, Tu-I ; Chen, Y.S.“Quiet Period (QP)

Tu- .

Scheduling Across Heterogeneous Dynamic Spectrum Access (DSA)-based Systems.” IEEE Trans.

(DSA)-

On Wireless Communications, Volume 11, P. 2796- P. 2805, Aug. 2012.

Constructed a testbed, by using USRP devices as secondary users, DVB-T signal as primary

user, and a feature detection method which exploit the cyclic prefix of OFDM signal

HONORS & LEADERSHIP

Passed the PhD Screening Exam (1st stage of Qualify) Dec./ 2012

NTU Presidential Award (ranking top 5% in a semester 5/250) June/ 2010

Contact this candidate