Christophe Basset

** **** **** **

Altadena, CA91001

USA Phone : +1-626-***-****

E-mail: abqswr@r.postjobfree.com

Work Experience

**** - **** ***** ******* - ********, CA

Senior lead designer - System integration engineer - Project manager

Lead a team of designers to develop advanced CMOS image sensors.

Successfully lead $500K to over $1M projects from start to finish with high customer satisfaction.

Responsible for all phases of the projects: project planning, financials, technical oversight, design (emphasis on digital development and integration), interface with customer and foundry (both on management and technical levels), test system development, sensor bring-up, technical support, etc.

Senior designer

Design of digital control and datapath circuits for on-chip and external CMOS image sensors (4T, 5T architectures).

High degree of familiarity with image sensors timing, readout architectures, data formats, communication interfaces, etc.

On-chip circuits including specifications, RTL development, verification as well as physical implementation with Cadence tools (RC, Encounter, Virtuoso, etc.)

Off-chip controllers implemented on Xilinx FPGAs (Virtex 4/5/6).

Senior scientist

Characterization of CMOS image sensors; research on applying image processing algorithms in real-time architectures for on-chip implementation (e.g. tone mapping).

2000 - 2006 Jet Propulsion Laboratory - Pasadena, CA

Active Pixel Sensor group.

Collaborative work with Caltech's Vision Laboratory.

Advisors: Prof. Pietro Perona (Caltech) and Dr. Bedabrata (Mithu) Pain (JPL)

Development of a computational CMOS imager with an integrated general-purpose filter for early image processing. This "system on a chip" combines a CMOS (Active Pixel Sensor) imager with an analog computing unit that performs a convolution between a digital kernel and each frame.

See my research homepage for more information.

1997 - 2006 California Institute of Technology - Pasadena, CA

Physics Department.

Teaching Assistant.

Freshman Physics lab: Ph3.

Analog electronics lab for undergraduate and graduate students: Ph5/105.

May - August 1997 Advanced PC Technologies - Bièvres, France

Internship in a research and development team.

Design of a set-top box for IEEE-1394 serial bus.

Study of the digital video standards.

CAD with .

Sept - Dec 1996 Undergraduate Project at ESIEE

Design of a video-caption interface board for image processing.

CAD with Compass and Xilinx tools.

Implementation on a Xilinx FPGA.

Apr - July 1996 Micro Module Systems - Cupertino, CA

Internship in the failure-analysis lab.

Localization and study of shorts on aluminum and ceramic wafers.

Probe-testing and analysis of defective wafers.

July - August 1994 Trillium Digital Systems - Los Angeles, CA

Internship. Programming in ANSI C.

Education

1998 - 2007 California Institute of Technology - Pasadena, CA

Ph.D. in Electrical Engineering in the

Vision Laboratory.

Collaborative work with NASA's

Jet Propulsion Laboratory as part of the

Active Pixel Sensor group.

Advisors: Prof. Pietro Perona (Caltech) and Dr. Bedrata (Mithu) Pain (JPL)

Defended April 6, 2007. Degree awarded in June, 2007.

Research interests:

Mixed-signal Full-custom ASIC design, computer vision (hardware, software, algorithms CMOS imagers (Active Pixel Sensor), system-on-a-chip.

See my for more information.

1997 - 1998 California Institute of Technology - Pasadena, CA

Master of Science in Electrical Engineering.

Emphasis on Computer Vision and digital design.

Transistor-level description of a fully asynchronous ARM-like processor. (group project) FPGA implementation of a tracking system based on image centroiding calculations. 3-D Photography. Scanning of three dimensional objects using a camera and a laser beam

Degree awarded in June, 1998.

1993 - 1997 Ecole Supérieure d'ingénieurs en Electrotechnique et Electronique (E.S.I.E.E.) - Noisy-le-Grand, FRANCE.

Undergraduate studies

Specializing in Electronics and Microelectronics. Emphasis on Digital logic and circuit design.

Electrical Engineering degree awarded in June, 1998.

1992 - 1993 Lycée Fénelon, Paris, France

Engineering school preparation year (Math Sup). Intensive Mathematics and Physics

program.

June 1992 Baccalauréat C - Lycée Fénelon,

Paris, France

French national secondary school-leaving certificate with emphasis

in Mathematics and Physics awarded with distinction.

Computer skills

Programming Languages

Verilog Synthesizable for ASIC implementation and FPGA, timing closure; verification testbenches, post-place and route simulations...

Matlab High-level system simulation; image processing algorithms validation

LabView Developed test environments for custom circuits: pattern generation, analog and digital data acquisition, display and processing of data

C/C++ Including OpenGL/GLUT graphics programming

Assembly ARM, 680x0, PIC...

CAD Tools

Digital design: RTL Compiler, HAL, Encounter, NC-verilog.

Analog design: Virtuoso schematic and layout, spectre.

HDL and schematics; simulation; FPGA programming

Schematics, iLayout of PCBs for customer low-noise test boards.

Languages

French Native language.

English Fluent. Living in the USA since 1997 (US citizen).

Extra Curricular Activities

Sports

Cycling Long distance road touring.

SCUBA Rescue Diver certification

Music

Acoustic Guitar Advanced; classical, Baroque, Flamenco... ResourcesResume also available in Adobe Acrobat format:

This document: http://www.vision.caltech.edu/basset/resume/index.php

Contact: abqswr@r.postjobfree.com

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