Design Project

S IDDHARTH S BHARGAV

Apt *B,**** W Adams Blvd., Los Angeles, California, 90007 abqouo@r.postjobfree.com / abqouo@r.postjobfree.com cell: 213-***-****

Education:

PhD Student - University of Southern California VISA STATUS: F-1 Student

Department of Electrical Engineering

Advisor: Prof. Young H Cho.

Visiting Graduate Student California Institute of Technology

Department of Computer Science

Masters of Science University of Southern California May, 2010

Department of Electrical Engineering GPA: 3.75/4

Graduate Courses: MOS VLSI Circuit design, VLSI System Design I & II, Computer Syste m Organization, Asynchronous VLSI Design,

Diagnosis and Design of Reliable Digital Systems, Solid State Processing and Integrated Circuits Laboratory, Computer Aided Design of

Digital Systems II, Introduction to communication systems.

Courses at Caltech: Research in Computer science.

Bachelors of Engineering Visweshwaraiah Tech Univ, India June 2006

Electronics and Communication Engineering FIRST CLASS WITH DISTINCTION

Academic Projects:

Tools Used : NetFPGA design suite

1) Simulation of Wireless network nodes on NetFPGA SUMMER 2011

Implemented hardware to simulate packet forwarding in wireless network nodes with packet dropping probability and successfully

demonstrated expected results at the NetFPGA summer camp 2011, Stanford University. (BEST PROJECT AWARD)

2) Automated Clock Gating Tools used: Berkeley SIS, C FALL 2010

Automatically synthesized and produced a gate-level net list that is optimally clock gated to minimize power over area overhead metric.

3) Soft error tolerant asynchronous memories Tools used: Cadence Virtuoso, HSPICE and Calibre SUMMER 2010

Designed schematic, layout of SEU tolerant SRAM with 6*64 row decoder, read/write circuitry, sense amplifiers etc.

4) DDR2 Controller Design Tools used: NCSim, NC-Verilog, Synopsys DC FALL 2009

VerilogHDL design of DDR2 controller using Denali s 512Mb software model based on JEDEC specs and Synthesized in 0.18um

technology using Synopsys DC.

5) 5 stage Pipelined Processor design Tools used: EPD FALL 2008

Designed a 5 stage pipelined processor to support in order execution of MIPS instructions taking care of RAW and Branch hazards.

6) 2.048Kb SRAM Design in 0.18um tech. Tools used: Cadence Composer/Virtuoso, HSPICE, Nanosim SPRING 2009

Designed schematic, layout of SRAM with 6*64 row decoder, precharge, read/write c ircuitry, sense amplifiers, etc.

7) Hardware Design of 16-Bit Motion Estimator for a DSP Tools used: Cadence Virtuoso, HSPICE, Nanosim SPRING 2009

Designed Schematic, floor planning, layout of a 470MHz 16-bit ME kernel in 0.18um tech. using 7 bit incrementer, 4Kb data memory using

SRAM, 16 bit absolute subtractor & difference accumulator using 24 bit Han Carlson tree adder. (BEST PROJECT AWARD)

8) Test Generation system for a FPGA chip family Language used: C FALL 2009

Designed an ATE for a circuit given in ISCAS 85 format. The major components of the test generation system designed and integrated are

Preprocessor, Logic simulator, Fault simulator and an ATPG.

9) IC Chip fabrication and electrical characterization Tools used: IC fabrication lab, USC. FALL 2008

Fabricated and characterized MOS resistors, capacitors, diodes and FET with a feature size of 1.2 m on Si (100) P -type substrate wafer.

10) Design of Digital Neural Network Tools used: Cadence Composer/Virtuoso, HSPICE

Designed a digital neural network in both schematic and layout using cadence in 0.18um technology.

11) 4X4 Asynchronous crossbar Tools used: ModelSim SPRING 2009

Designed a 4X4 crossbar using VerilogCSP and optimized design for lowest latency.

Jan June 2006

12) Shared Streaming - Indian Institute of Science, Bangalore. Tools used: Visual C++

Designed and integrated a streaming VOIP application into an existing peer-to-peer communication application.

Work Experience

(May 2009 Aug 2010)

Research Assistant under Prof.Alain J Martin, Department of Computer Science, Caltech.

1. Designed robust soft error tolerant asynchronous memories and characterization of sub-nanometer technologies using foundry data,

HSPICE and Cadence Composer/Virtuoso, Synopsis Calibre.

2. Analysis of manufacturing variations in sub nanometer technologies and their impact on VLSI design synthesis.

Research Assistant Information Sciences Institute, University of Southern California (May 2011 Till Date)

Currently, I work with Prof.Young Cho for the project green edge networks in implementing uninstrumented power measurement.

Teaching Assistant University of Southern California (Jan 2010 Till Date)

I have been a Teaching Assistant for

1. EE552: Asynchronous VLSI design(Prof.Jon Dama)- responsible for help students implement course projects and labs,

2. EE658: Diagnosis and Design of Reliable Digital Systems(Prof.Melvin Breuer)- Mentor students in the coursework and help them

implement course projects which included automatic test generation, fault simulation and fault diagnosis.

3. EE 577B: VLSI System Design (Prof.Shahin Nazarian) - Designed assignments, labs, quizzes. Developed lab to introduce DFT compiler

to students: created DFT compiler scripts and tutorial.

4. EE599 Network Processor (Prof Young Cho) - Mentor students in the coursework and help t hem implement course projects which

included building network processors over NetFPGA platform.

Project Engineer Manufacturing Solutions, Wipro Technologies (Aug 2006 June 2008)

Developed middleware interfaces, along with system administration and training project engineers on software design tools.

As a business development engineer at Wipro, I was responsible for creating research dockets to assist the sales and decision cycles.

Publications

1. Measuring Power Digitally with Numerical Analysis Siddharth Bhargav, Young H. Cho, ACM Sigmetrics, London, 2012.

2. Reliable Minimum Energy CMOS Circuit Design Sean Keller, Siddharth Bhargav, Alain J.Martin,VARI 2011.

3. Presented whitepaper titled Supplier Relationship Management- a Key differentiator in Aerospace manufacturing at Indian

Institute of Management, Bangalore at IMRC- Global Supply chain Conference.

4. Presented Technical paper titled Black Box Neo Paradigm in Wipro Technologies

5. Submitted a whitepaper on Efficient Automobile telemetry at Indian Institute for Science.

Honors and Awards

Won the best project award at the NetFPGA summer camp 2011, Stanford University.

Won the design contest for the project 16 bit motion estimation kernel of a DSP at USC.

Awarded Thanks a Zillion Award in Wipro Technologies at the General Motors CTO meet.

Secured FIRST place in State- Level swimming competition.

Awarded Third Prize in violin recital in Karnataka Region cultural Meet.

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