| Resume alert | Resumes 51 - 60 of 127 |
Design Data
Los Angeles, CA
... Digital Computers (EE-658) Integrated Memory Devices and Technology (EE- 599) Technical skills: Programming Languages: Verilog, Perl, VHDL, TCL, System Verilog, MATLAB, C Packages/Tools: Cadence Tools(Virtuoso,Spectre), Xilinx ISE Design Suite, ... - 2016 Jul 08
... Digital Computers (EE-658) Integrated Memory Devices and Technology (EE- 599) Technical skills: Programming Languages: Verilog, Perl, VHDL, TCL, System Verilog, MATLAB, C Packages/Tools: Cadence Tools(Virtuoso,Spectre), Xilinx ISE Design Suite, ... - 2016 Jul 08
Secondary School Engineering
Pasadena, CA
... PROJECT WORK Enhanced Memory Reliability against Multiple upsets using Decimal Matrix Code TOOLS USED: XILINX ISE-9.1 AND MODEL SIM 6.3 TECHNICAL SKILLS Verilog &VHDL program using Xilinx P-spice software micro wind tool tanner Application packages- ... - 2016 Jun 19
... PROJECT WORK Enhanced Memory Reliability against Multiple upsets using Decimal Matrix Code TOOLS USED: XILINX ISE-9.1 AND MODEL SIM 6.3 TECHNICAL SKILLS Verilog &VHDL program using Xilinx P-spice software micro wind tool tanner Application packages- ... - 2016 Jun 19
Design Project
Pasadena, CA
... Programming in C and C++ languages, HDL and Verilog languages. Strong analytical, problem solving skills. EDA Tools: Cadence Virtuoso® Schematic Editor L Editing, Virtuoso® Analog Design Environment L Editing. Virtuoso® Assura RC, Virtuoso® Assura ... - 2016 May 28
... Programming in C and C++ languages, HDL and Verilog languages. Strong analytical, problem solving skills. EDA Tools: Cadence Virtuoso® Schematic Editor L Editing, Virtuoso® Analog Design Environment L Editing. Virtuoso® Assura RC, Virtuoso® Assura ... - 2016 May 28
Industrial Training Project
Pasadena, CA
... COMPUTER SKILLS Programming Languages : VHDL, Verilog, C and C++. Simulation tools : Xilinx, Microwind, Tanner. TECHNICAL SKILLS Participated 2 days workshop on Cyber security and Ethical hacking Participated 1 day workshop on Employability of ... - 2016 May 11
... COMPUTER SKILLS Programming Languages : VHDL, Verilog, C and C++. Simulation tools : Xilinx, Microwind, Tanner. TECHNICAL SKILLS Participated 2 days workshop on Cyber security and Ethical hacking Participated 1 day workshop on Employability of ... - 2016 May 11
Electrical Engineering
Los Angeles, CA
... Verilog and State Machine University of California, Los Angeles, CA Fall 2015 • Wrote in Verilog for state machine and wrote test bench to test the result. Noise Filtering and Object Segmentation University of Washington, Seattle, WA September ... - 2016 May 04
... Verilog and State Machine University of California, Los Angeles, CA Fall 2015 • Wrote in Verilog for state machine and wrote test bench to test the result. Noise Filtering and Object Segmentation University of Washington, Seattle, WA September ... - 2016 May 04
Electrical Engineering Design
Los Angeles, CA
... India July 2013 Bachelor of Engineering, Electronics Engineering GPA: 71.5/100 TECHNICAL SKILLS Programming Languages: Verilog, C, Perl, Python, VHDL Tools: ModelSim, Cadence Virtuoso Layout Editor, NCSim, SoC Encounter, Synopsys Design Compiler, ... - 2016 Apr 29
... India July 2013 Bachelor of Engineering, Electronics Engineering GPA: 71.5/100 TECHNICAL SKILLS Programming Languages: Verilog, C, Perl, Python, VHDL Tools: ModelSim, Cadence Virtuoso Layout Editor, NCSim, SoC Encounter, Synopsys Design Compiler, ... - 2016 Apr 29
Engineer Design
Los Angeles, CA
... Tools: Behavioral Simulation - Synopsys VCS, NCVerilog, Icarus Verilog, ModelSim, Canalyzer. Synthesis - Synopsys Design Compiler Gate Level Simulation - NCSim FPGA tools - Xilinx ISE and Vivado, Altera Quartus II Place & Route - Cadence Encounter ... - 2016 Apr 24
... Tools: Behavioral Simulation - Synopsys VCS, NCVerilog, Icarus Verilog, ModelSim, Canalyzer. Synthesis - Synopsys Design Compiler Gate Level Simulation - NCSim FPGA tools - Xilinx ISE and Vivado, Altera Quartus II Place & Route - Cadence Encounter ... - 2016 Apr 24
Design Engineering
Canyon Country, CA, 91351
... SKILLS FPGA Implementation: Proficient at both Verilog and VHDL. Practical experiences with Virtex-7, Virtex-6, Virtex-5, ZYNQ-7000, Spartan-6, Spartan-3. Ability of Dynamic Partial Reconfiguration, which lets to partially reprogram different parts ... - 2016 Apr 15
... SKILLS FPGA Implementation: Proficient at both Verilog and VHDL. Practical experiences with Virtex-7, Virtex-6, Virtex-5, ZYNQ-7000, Spartan-6, Spartan-3. Ability of Dynamic Partial Reconfiguration, which lets to partially reprogram different parts ... - 2016 Apr 15
Engineer State University
Los Angeles, CA
... TECHNICAL SKILLS AND TOOLS Programming: C, C++, A51 assembly, VHDL, Verilog, ARM assembly, python. Software Tools and Packages: µVision – Keil Software, IAR Embedded Workbench, Silicon labs, Arduino, AVR studios, CadSoft Eagle, Xilinx ISE, Vivado, ... - 2016 Apr 04
... TECHNICAL SKILLS AND TOOLS Programming: C, C++, A51 assembly, VHDL, Verilog, ARM assembly, python. Software Tools and Packages: µVision – Keil Software, IAR Embedded Workbench, Silicon labs, Arduino, AVR studios, CadSoft Eagle, Xilinx ISE, Vivado, ... - 2016 Apr 04
Java Developer Computer Engineering
Los Angeles, CA
... + Developed a technical manual (chip specifications) for a SOC design (programmed in Verilog). The chip was composed of an 8-bit microcontroller (PicoBlaze) and UART interface which was developed and tested using the Nexys 2 FPGA board. The software ... - 2016 Feb 15
... + Developed a technical manual (chip specifications) for a SOC design (programmed in Verilog). The chip was composed of an 8-bit microcontroller (PicoBlaze) and UART interface which was developed and tested using the Nexys 2 FPGA board. The software ... - 2016 Feb 15