| Resume alert | Resumes 11 - 20 of 681 |
Project Design
Bengaluru, KA, India
... Paper publications: Design of shift registers using latches at IRJET publications 2016 Skills VLSI Domain Skills HDL Verilog. HVL System Verilog. EDA tools Questa sim, ISE, Tanner tool, Microwind, Xilinx. Domain Knowledge Digital electronics, VLSI ... - 2018 Jan 23
... Paper publications: Design of shift registers using latches at IRJET publications 2016 Skills VLSI Domain Skills HDL Verilog. HVL System Verilog. EDA tools Questa sim, ISE, Tanner tool, Microwind, Xilinx. Domain Knowledge Digital electronics, VLSI ... - 2018 Jan 23
Engineer Technical Support
Bengaluru, KA, India
... 3, Issue 2, pp 224-232, April – June 2015 Technical knowledge Assembly / Programming Languages: Verilog, VHDL, Basic C. Application Tools: Cadence virtuoso, Xilinx, Keil, Matlab, Mentor graphics. Operating Systems: Windows XP, Windows 7, Windows 8, ... - 2018 Jan 12
... 3, Issue 2, pp 224-232, April – June 2015 Technical knowledge Assembly / Programming Languages: Verilog, VHDL, Basic C. Application Tools: Cadence virtuoso, Xilinx, Keil, Matlab, Mentor graphics. Operating Systems: Windows XP, Windows 7, Windows 8, ... - 2018 Jan 12
Microsoft Office Engineering
Bengaluru, KA, India
... Languages:VHDL & Verilog, Matlab, C. Knowledge about microcontroller and microprocessor. PROJECT REPORT Ultra power saving using android app and PWM technology. EXTRACURRICULAR ACTIVITIES Participated in the workshop on Implementation of new ... - 2018 Jan 05
... Languages:VHDL & Verilog, Matlab, C. Knowledge about microcontroller and microprocessor. PROJECT REPORT Ultra power saving using android app and PWM technology. EXTRACURRICULAR ACTIVITIES Participated in the workshop on Implementation of new ... - 2018 Jan 05
Engineering Test Cases
Bengaluru, KA, India
... ●Languages : Verilog, C ●Distributed Control System : CENTUM VP Engineering and Maintenance (YOKOGAWA) Beginner in:- ●PLC : STARDOM PLC (Yokogawa) ●SCADA : Fast/Tools SCADA System (Yokogawa) ●Basics of Field Instruments for Process Control ●Basics ... - 2017 Dec 14
... ●Languages : Verilog, C ●Distributed Control System : CENTUM VP Engineering and Maintenance (YOKOGAWA) Beginner in:- ●PLC : STARDOM PLC (Yokogawa) ●SCADA : Fast/Tools SCADA System (Yokogawa) ●Basics of Field Instruments for Process Control ●Basics ... - 2017 Dec 14
Security Engineering
Bengaluru, KA, India
... 75 % SSLC Government Higher Secondary School,Jolarpettai State Board 2010 58 % TECHNICAL SKILLS Programming Language : C, Verilog HDL Tolls : TSPICE, XILINX PROVEN CAPABILITIES : Good team Player Active listener Discharge duties with commitment and ... - 2017 Dec 05
... 75 % SSLC Government Higher Secondary School,Jolarpettai State Board 2010 58 % TECHNICAL SKILLS Programming Language : C, Verilog HDL Tolls : TSPICE, XILINX PROVEN CAPABILITIES : Good team Player Active listener Discharge duties with commitment and ... - 2017 Dec 05
Engineering Design
Bengaluru, KA, India
... COMPUTER PROFICIENCY: • Programming Languages : C,C++,Verilog HDL,VHDL,SPICE. • Software Tools : MS Office, Xilinx ISE 8.2i, Modelsim,HSpice,Tanner EDA, MATLAB, SPSS. PROJECT DETAILS: Under Graduate: • FPGA IMPLEMENTATION OF SCALABLE ENCRYPTION ... - 2017 Nov 22
... COMPUTER PROFICIENCY: • Programming Languages : C,C++,Verilog HDL,VHDL,SPICE. • Software Tools : MS Office, Xilinx ISE 8.2i, Modelsim,HSpice,Tanner EDA, MATLAB, SPSS. PROJECT DETAILS: Under Graduate: • FPGA IMPLEMENTATION OF SCALABLE ENCRYPTION ... - 2017 Nov 22
Project Engineering
Bengaluru, KA, India
... 2008 78% TECHNICAL SKILLS Programming languages : C, Verilog Subject of interest : VLSI (Physical design), Logic Design Tools and Design :CADENCE,LABVIEW, ORCAD PCB Designing ENGINEERING PROJECT DETAILS Title :" Malignant Melanoma Detection Based On ... - 2017 Nov 20
... 2008 78% TECHNICAL SKILLS Programming languages : C, Verilog Subject of interest : VLSI (Physical design), Logic Design Tools and Design :CADENCE,LABVIEW, ORCAD PCB Designing ENGINEERING PROJECT DETAILS Title :" Malignant Melanoma Detection Based On ... - 2017 Nov 20
Project Engineering
Bengaluru, KA, India
... Electronic and communication Engineering 55% 2017 K.N.S Institute of Technology, VTU Diploma in electronics engg (CTEVT BOARD NEPAL) 69% 2012 10th (SLC BOARD NEPAL) 62.88% 2008 Programming Languages :cpp, Verilog, system Verilog, embedded C,HDL ... - 2017 Nov 05
... Electronic and communication Engineering 55% 2017 K.N.S Institute of Technology, VTU Diploma in electronics engg (CTEVT BOARD NEPAL) 69% 2012 10th (SLC BOARD NEPAL) 62.88% 2008 Programming Languages :cpp, Verilog, system Verilog, embedded C,HDL ... - 2017 Nov 05
verilog,VHDL,c, vb,matlab
Bengaluru, KA, 560001, India
... TECHNICAL ACQUAINTANCE IDEs / Tools : Cadence, Mentor graphic, Modelsim, Xilinx, MATLAB Languages : Basic C, C++, VB,Verilog, VHDL Assembly Languages : Microcontroller, Microprocessor Databases : Oracle Operating System : Windows XP, Windows 7,Linux ... - 2017 Oct 27
... TECHNICAL ACQUAINTANCE IDEs / Tools : Cadence, Mentor graphic, Modelsim, Xilinx, MATLAB Languages : Basic C, C++, VB,Verilog, VHDL Assembly Languages : Microcontroller, Microprocessor Databases : Oracle Operating System : Windows XP, Windows 7,Linux ... - 2017 Oct 27
Design Engineering
Bengaluru, KA, India
... • Extensive experience in writing RTL models in Verilog HDL and test bench’s in System Verilog and UVM. • Experience in using industry standard EDA tools for the front-end design. Educational Qualification • Advanced VLSI Design and Verification ... - 2017 Oct 16
... • Extensive experience in writing RTL models in Verilog HDL and test bench’s in System Verilog and UVM. • Experience in using industry standard EDA tools for the front-end design. Educational Qualification • Advanced VLSI Design and Verification ... - 2017 Oct 16