RAKESH M KADANAGOUDRA contact info: 988*******
******************@*****.***
Career Objective
To seek a position as a VLSI engineer in an organization, where I can contribute my skills to organizational development as well as my professional career growth. Overview
• Good understanding of the ASIC and FPGA design flow.
• Extensive experience in writing RTL models in Verilog HDL and test bench’s in System Verilog and UVM.
• Experience in using industry standard EDA tools for the front-end design. Educational Qualification
• Advanced VLSI Design and Verification Course:
o From: Maven Silicon VLSI Design and Training Institute, Bengaluru o Duration: July 16- Pursuing (6 months).
• Bachelors of Engineering in Electronics and Communication o Government Engineering College, Raichur (VTU)
o Cumulative Percentage: 62.02%.
• Diploma in Electronics and Communication Engineering o CB Kolli Polytechnic, Haveri (DTE)
o Cumulative Percentage: 67.48%.
• 10th STD (KSEEB)
o SJS High School, Sudambi.
o Cumulative Percentage: 71.04%.
Tool and Technical Skills
HDL : Verilog HDL
HVL : System Verilog
TB Methodology : UVM
EDA Tools : XILINX-ISE, Questa Verification Platform, Riviera-PRO Protocols : AHB-APB BRIDGE
Domain : ASIC/FPGA front-end design and back-end design Knowledge : Static Timing Analysis, RTL Coding, FSM based design, ASSERTION, Code Coverage, Functional Coverage,
Simulation, Synthesis
Operating Systems : Windows and Linux.
Projects
[1] Router 1x3-RTL design and Verification
HDL: Verilog
HVL: System Verilog
TB Methodology: UVM
EDA Tools: Riviera-PRO and Xilinx-ISE
Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2.
• Architected the class based verification environment using SV and UVM
• Prepared various test cases and RTL using SV and UVM
• Involved in generating functional and code-coverage for the RTL verification sign-off Academic Projects and Seminar details
• Embedded Microcontroller Lab Trainer Kit
• Solar Oxygen Tree
• Seminar on VANET
Strength
Good interpersonal and Communication Skills fast learner, Ability to pick up any subject in short period, Confidence in my effort and hard work, Good team co-ordinate and team Player.
Personal Profile
Name : Rakesh M Kadanagoudra
Father’s Name : Mukanagoudra
Date of Birth : 26/05/1991
Gender : Male
Marital Status : Single
Mother Tongue : Kannada
Nationality : Indian
Languages Known : Kannada, English, Hindi, Telugu
Permanent Address : At : Chikkabasur -581120, Tq : Byadgi, Dist : Haveri Declaration
I hereby declare that the information given above is true to the best of my knowledge and belief.
Date:
Place Rakesh M Kadanagoudra