Nikitha N

Assistant professor (** Years’ experience)

Mobile : +91-890*******

Email : ac35lh@r.postjobfree.com

LinkedIn: https://www.linkedin.com/in/nikithan

Objective

To be associated with the organization that provides me bondless growth opportunities to enhance my skills and be fruitful to the organization.

Summary

In 2016, I completed post-graduated with master degree in VLSI design & embedded system with 75% from Bellary Institute of Technology and Management, Bellary, Karnataka.

In 2011, I completed my graduation in electronics & communication with 62% from Rao bahadhur y mahabaleshwara engineering college.

Currently working as assist.prof in SCTIT college Bangalore.

Paper publications: Design of shift registers using latches at IRJET publications 2016

Skills

VLSI Domain Skills

HDL Verilog.

HVL System Verilog.

EDA tools Questa sim, ISE, Tanner tool, Microwind, Xilinx.

Domain Knowledge Digital electronics, VLSI

Experience (03-years)

Worked as a lecturer in RYMEC from June 2012 to 2013 December engineering college handled subjects like digital logic, electronic instrumentation, microelectronics circuits’, analog communications and Processor labs..

From 2017 august started working as an asst.prof in SCTIT College Bangalore handled wireless communication & teal time operating systems.

Projects

BE Academics Project

Project Title: “VOICE TO TEXT GENERATING DEVICE”

Duration: 4 months (in 8th SEM)

Team Size: 4

Programming language: AT89S52 MICRONCTROLLER

Description: To convert voice signal into text format using a matlab software where database will be created and it will be stored in microcontroller. Whenever voice signal is sent through microphone the signal will be converted to text format making use of both matlab and microcontroller the final result will be displayed on an LCD screen.

Project at Q-Spider

Project Title:“ACTI-TIME”

Description : ACTI-TIME is time collection software that is streamlined for billing and invoicing purposes. ACTI-TIME allows time tracking for customer and project related tasks. After being collected the data can then be exported for invoice generation. It has The five main activities when working with actiTIME are Registration of time expenses, Task, project, and customer management, Reporting System administration, Creation of invoices in QuickBooks.

M.tech Academics Project

Project title: “Front end design of shift registers using pulsed latches”

Description: The project is based on designing a shift registers using pulsed latches instead of flip-flops which helps in reduction of power consumption, area and delay. I made use of a multiple non over lapping delayed clock pulse signals which helps in reduction I number of clock pulses. Here we designed for 4bit & 256 bit which is shifted for ever clock pulse signal. The design is done by Xilinx and modelsim for synthesis and simulation.

Seminars

Wireless LAN.

Automaive cars.

Regaining rust in VLSI Design: DFTR techniques

My Strengths

Willing to work under pressure

Good Team Player, Quick learner, Well-co-ordination with colleagues and Management.

Education

Course

Specialization/Stream

Percentage/C.G.P.A

Year of Passing

M. tech

VLSI design & embedded system

.

75%

2016

B.E

Electronics & communication

62%

2011

Higher Secondary Education

II- PUC

54%

2007

Secondary Education

SSLC

68.48%

2005

Personal details

Date of Birth : 23-11-1989

Gender : Female

Father Name : Jayadev goud N

Mother Name : Girijamma N

Nationality : Indian

Marital Status : Married

Interests

Gardening, embroidery works, reading books, exploring new things, travelling.

References

References can be provided on request.

Contact this candidate