Utkarsh Srivastava
Email Id :- **************@*****.***
Contact: - +91-958*******
Objective: - To utilize my knowledge, technical and managerial skills and team building approach for the effective growth of the organization.
Qualifications:-
●B.Tech (Electronics and Communication Engineering) with aggregate 62.78% from ABES Engineering College, Ghaziabad (2013-17 Batch).
●12th with aggregate 82.6% from BBL Public School, Bareilly (C.B.S.E.) in 2013.
●10th with 7.6 CGPA from St. Mary’s Convent School, Gajraula (C.B.S.E.) in 2011.
●Pursuing** Industrial Automation Training from YOKOGAWA India Limited.
Competency:
●I have an interest in Automation and Digital Electronics.
●Languages : Verilog, C
●Distributed Control System : CENTUM VP Engineering and Maintenance (YOKOGAWA)
Beginner in:-
●PLC : STARDOM PLC (Yokogawa)
●SCADA : Fast/Tools SCADA System (Yokogawa)
●Basics of Field Instruments for Process Control
●Basics of Plant Instrumentation.
●Beginner to LabVIEW Automation
●Simulation tools : Xilinx ISE 14.7
Professional Skills:
●Good verbal and personal communication skills.
●Analytical skills.
●Ability to make sound decisions.
●Organizational and Prioritization skills.
Technical Training:
Organization: JUBILANT Agri and Consumer Products, Gajraula
Duration : 11th June, 2016 – 15th July, 2016
Description : The training was in Instrumentation Department.
Learning : The application of PLCs and VFD in industry and Working of packaging machine.
Organization: Pine Training Academy, Ghaziabad
Duration : October, 2015 – March, 2016
Description : Digital Design using Schematics, Verilog and Implementation of FPGA
Learning : Xilinx ISE 14.6, Verilog and FPGA Board
Organization*: YOKOGAWA Technical School
Duration : 11th December, 2017 – 2nd February, 2018
Description : Industrial Automation Training in DCS, PLC, SCADA, Basics of Plant Instrumentation. Learning :
1.DCS Engineering and Maintenance : Centum VP
2.STARDOM PLC
3.Fast/Tools SCADA SYSTEM
4.Basic Field Instruments for Process Control
Projects:
Project Name: Design and Implementation of FFT on FPGA
Team Size : 3
Description : Verification of design under test by generating all possible test cases, using test benches. The test benches are coded using Verilog HDL.
Learning : Verilog, FPGA Board
Project Name: FPGA Implementation of BID based Floating Point Multiplier.
Team Size : 4
Description : Decimal floating-point (DFP) arithmetic is important in many applications because of its ability to represent decimal fractions exactly and to mimic manual calculations that perform decimal rounding.
Achievements and Awards:
●Second Prize Robo-Race in GENERO (Annual Techno-Cultural Fest of ABESEC).
●Second runner-up in Table Tennis in CBSE Cluster 2009 and 2010.
●Winner FSLG interschool tournament Table Tennis 2010 and 2009
●First position in TABLE TENNIS in Annual Inter College Sports Meet “UTSAAHA-2014”.
●Second in Art, Science and Photography School Exhibition 2012
Interests:
●Playing Table Tennis
●Swimming
●Listening music.
●Educating the under-privileged children.
Personal Details:
●Father’s Name : Mr. Brijendra Kumar Srivastava (Advisor in Tata Chemicals Ltd.)
●Date of Birth : March 7, 1995
●Address : H.No-537/122, Maharaja Agrasen Nagar, Tadi Khana, Sitapur Road, Lucknow, Uttar
Pradesh