Verilog, system verilog, uvm

VIJAYA LAKSHMI K

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Porumamilla, KADAPA, Email: ********@*****.***

A.P, India – 516505 Mobile: +918*********

Summary of Qualifications:

Good understanding of the ASIC and FPGA design flow

Experience in writing test benches in SystemVerilog and UVM

Very good knowledge in verification methodologies

Experience in using industry standard EDA tools for the front-end design and verification.

Experience in writing RTL models in Verilog.

VLSI Domain Skills:

HDL: Verilog

HVL: SystemVerilog

Verification Methodologies: Coverage Driven Verification Assertion Based Verification - SVA

TB Methodology: UVM

Protocols: SPI, ETHERNET, ROUTER

EDA Tool: Questasim and ISE

Domain: ASIC/FPGA front-end Design and Verification Knowledge: Simulation, Code Coverage, Functional Coverage, Synthesis, Static Timing Analysis, ABV- SVA,

RTL Coding, FSM based design.

Professional Qualification:

Maven Silicon Certified Advanced VLSI Design and Verification course From Maven Silicon VLSI Design and Training Center, Bangalore June 2015 – Dec 2015

ACADEMIC EDUCATION:

Bachelor of Engineering, Madanapalle Institute of Technology & Science, Madanapalle Jawaharlal Technological University, Ananthapur, A.P, India Discipline: Electronics & Communication Engineering Percentage: 78% First Class

Year: May 2015

Achievements:

Certified from BSNL, Proddatur.

Participated as a volunteer in National level sports & games at Govt. Polytechnic for Women, Kadapa.

Experience:

Project Intern, Maven Silicon

Six months experience in front end design and verification June 2015 – Dec 2015

VLSI Projects:

[1] Router 1x3 – RTL design and Verification

HDL: Verilog

HVL: SystemVerilog

TB Methodology: UVM

EDA Tools: Questasim and ISE

Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2. Responsibilities:

Architected the design

Implemented RTL using Verilog HDL.

Architected the class based verification environment using system Verilog

Verified the RTL model using SystemVerilog.

Generated functional and code coverage for the RTL verification sign-off

Synthesized the design

[2] SPI Controller Core - Verification

HVL: SystemVerilog

TB Methodology: UVM

EDA Tools: Questasim

Description: The SPI IP core provides serial communication capabilities with external device of variable length of transfer word. This core can be configured to connect with 32 slaves. Responsibilities:

Architected the class based verification environment in UVM.

Verified the RTL module using System Verilog.

Generated functional and code coverage for the RTL verification sign-off.

[3] PCS – RTL design and Verification

HDL: Verilog

EDA Tools: Questa and ISE

Description: 1000BASE-X PCS provides all services required by the GMII, including

Encoding (Decoding) of GMII data octets to (from) ten-bit code-groups (8B/10B) for communication with the underlying PMA.

Generating Carrier Sense and Collision Detect indications for use by PHY’s half duplex clients.

Managing the Auto-Negotiation process.

Responsibilities:

Architected the design and Implemented the RTL using Verilog HDL.

Verified the RTL using SystemVerilog.

Generated code coverage for the RTL verification sign-off.

Synthesized the design.

[4] AXI-4 Protocol - Verification

HVL: SystemVerilog

TB Methodology: UVM

EDA Tools: Riviera_Pro

Description: The AXI IP core provides write/read channels communication with slave device. This protocol having total 5 channels. AXI-4 provides separate address/control and data phases. It supports for unaligned data transfers, using byte strobes. Responsibilities:

Architected the class based verification environment in UVM.

Verified the RTL module using System Verilog.

Generated functional and code coverage for the RTL verification sign-off. Engineering Project

Project Title : Arduino Based Human Computer Interface for 3-D Image Visualization.

Organization : MITS College

Platform Used : Arduino, MATLAB.

Contribution : Team Leader

Description : To rotate the image by using accelerometer in 3- Dimensional view without using mouse.

DECLARATION:

I hereby declare that the above furnished information is true up to my knowledge and I will solely be responsible for any discrepancy found in them. Place: Bangalore.

Date: (K VIJAYA LAKSHMI)

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