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Project Engineering

Location:
Bengaluru, KA, 560001, India
Salary:
4 LPA
Posted:
March 30, 2016

Contact this candidate

Resume:

Kiran J P

Mobile: +91-720*******

Email-ID: *********@*****.***

OBJECTIVE

To succeed in an environment of growth and excellence and earn a job which provides me job satisfaction and self development and help me achieve personal as well as organization goals.

QUALIFICATION

Double Degree : VLSI Design and Embedded System.

University : Visvesvaraya Technological University, Belagavi. College : BMS College of Engineering, Bengaluru.

ACADEMIC DETAILS

Examination

Passed

Institutions

Attended

Board Percentage/CGPA

M.Tech BMSCE

Bengaluru

Visvesvaraya

Technological

University

Belagavi

Aggregate:71%

(upto 2nd sem)

B.E

(2014)

Dr. A.I.T

Bengaluru

Visvesvaraya

Technological

University

Belagavi

Aggregate:8.66

(79.1%)

12th

(2010)

Govt. PU College

Chickmagaluru

Karnataka

State

PCM-89.67%

10th

(2008)

SSRDHS

Chickmagaluru

Karnataka

State

91.06%

SKILL SET

Basic Knowledge in C, OOPS concept.

Knowledge about Logic Design.

Knowledge about Verilog,System Verilog,Perl.

CO CURRICULAR

Volunteer in college fest ‘SANSKRUTI’.

Participated in How to sell yourself and Nail the interview workshop. Volunteer in National conference NEWS-2014.

Participated in college Dramas and Miming.

PROJECT DETAILS:

Under Graduate Project Title: ’Quad Copter’.

Team Members : 4

Duration : 6 months

Tools Used : PIC µc, Zigbee, LM 35

Description: A Quad Copter is also known as Quad rotor helicopter is a multicopter that is lifted and propelled by four rotors. Quad copters are classified as rotorcraft as opposes to fixed wing aircraft, because their lift is generated by set of revolving narrow-chord foils.

Post Graduate Mini Project title: ‘Basic Gates Operation Using FINfet Technology’

Team Members : 4

Duration : 3 months

Tools Used : HSPICE, Cosmo Scope.

Description: In CMOS circuit, by varying the width and length of the gate it can be seen that the static and dynamic response obtained are too large. So, gate length is reduced from 180nm upto 16nm step by step. Below 16nm we have to use new technology called FINfet to get efficient static and dynamic responses. PERSONAL PROFILE

D.O.B : 04-06-1992

Father’s Name : Paramesh J V

Languages known : Kannada, English and Hindi

Hobbies : Drawing, Cooking, Solving SODUKU...



Contact this candidate