Assistant Design Engineer and working on iris recognition project
Resume:
CHETHAN G.
S/O GANGAPPA T.S.
Nethaji Nagar, Jallahalli cross, Phone: +91-779******* T.Dasarahalli, Bangalore-560057 E-mail: ************@*****.*** CAREER OBJECTIVE
A suitable position, which utilizes my skills and creativity with potential for growth, recognition and advancement. I have the interest, capability and motivation to play an effective role and carve a niche of myself in the organization I work for. STRENGTHS
Self-Confident, Team player, Innovative, Positive, Sincere, Quick Learner. Academic Qualifications
Course University/Board Batch Percentage/Grade
Master of
Sciences(M.S)
M.S. Ramaiah School of
Advanced Studies
[Coventry University, UK]
2015
A-(65%)= Merit
Bachelors of
Engineering(B.E)
Visvesvaraya Technological
University
2013
73.3%
2nd P.U.C / 12th
Grade
Dept. Of Pre-University
Education
2009 81.5%
10th Grade
(S.S.L.C)
Karnataka Secondary
Education Examination
Board
2007 84.64%
WORK EXPERIENCE
Working as an Assistant Design Engineer in Silicon Circuit Research Labs (SRL) Pvt Ltd since August 2015.
SKILLS
FPGA design flow from RTL design to programming a device using Xilinx Tool Hands-on experience in Physical design, Synthesis, Place & Route, Static Timing Analysis
Good Knowledge about ASIC Design flow and Implementation, Floorplan, Routing, CTS, DRC and LVS check flow and timing driven design flow. ASIC Design Tool: Cadence Tool chain
Simulation Tools: Modelsim, Isim, Simulink
Familiar with Verilog, VHDL and TCL script languages Custom IC design flow from Schematic design to Post layout simulation Operating System: Windows XP/7/8, Linux
Strong leadership, troubleshooting, and communication skills. PROJECT DETAILS
Project 1:
Title: Efficient Implementation of 3D-DWT based OFDM architecture on FPGA Description: Designing of a 3D DWT-IDWT architecture using lifting technique for OFDM system has been carried out. Then designing of 1D, 2D and 3D DWT architectures and BER, PSNR comparison of all the architectures are done. This analysis was performed using Matlab/Simulink Modeling and then RTL design and Synthesis using Xilinx is done. Finally Implementation of this design is carried out on FPGA.
Role and Responsibilities: Individual Undertaking of modeling, programming and testing is been carried out for M.S final year project.
Project 2:
Title: Hardware Framework for Intelligent Shopping Cart Description: In the urge of saving shopping time, a intelligent shopping cart is designed which scans and counts the products put into the cart by the customer thus saving the time wasted during standing in the queue for billing purpose. This is implemented on ARM based system with two phases of detection, first is with RF based scanning and then using IR sensor.
Roles and Responsibilities: Undertaking of modeling, programming and testing in a group of 5 for M.S group project.
Project 3:
Title: Design of I2C Protocol and FPGA, ASIC Implementation using Xilinx ISE and SoC Encounter respectively
Description: An FSM for I2C Protocol is designed using Verilog language and is synthesized in Xilinx ISE. The Design is implemented on FPGA using Xilinx Impact. Then netlist of the RTL design is generated using RC Encounter. Then physical implementation is carried out which includes Floor and Power Planning, Placement, CTS, Routing. Finally reports of Physical design are generated. Module Projects:
Design and Synthesis of Automatic Power Controller using Xilinx and NcSim.
Design, Physical Implementation and Verification of Real Time Clock using Xilinx along with Cadence Encounter.
Design and Full Custom Implementation of 8-bit ALU for 180nm using Cadence Virtuoso.
PERSONAL DETAILS
Name - Chethan G.
Father’s Name - Gangappa T.S.
Date of Birth - 22nd December 1991.
Sex - Male
Hobbies - Playing Cricket, TT, Chess, Volleyball.
Permanent Address - #92, 1st+ main, 1st cross, Nethaji Nagar, Jallahalli Cross, T.Dasarahalli,
Bangalore- 560057.
Nationality - Indian
Languages Known - English, Kannada & Hindi
(Read, Write & Speak)
DECLARATION:
I do here by confirm that the information given in this form is true to the best of my knowledge and belief.
(CHETHAN G.)
Date: __/__/2016
Place: Bangalore
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