Design Electrical Engineering

Chaitrasri Putter

Linkedin: https://www.linkedin.com/in/chaitra-shree-6972225a

Phone: 714-***-**** Email: acu4yz@r.postjobfree.com

Objective:

Looking for challenging opportunity in the field of FPGA/VLSI Designing and verification (Backend designer) and Digital System Design where my skill sets help me grow and expand the company.

Education:

Masters of Science, Electrical Engineering May 2016

California State University, Fullerton GPA- 3.2

Bachelor of Engineering, Electrical Engineering May 2013

Visvesvaraya Technological University, India GPA- 3.5

Technical Skills:

Language: VHDL, Verilog, System Verilog, SystemC, Perl

EDA Tools: Cadence (Virtuoso schematic/Layout editing), Microwind, Chip scope, Modelsim, Xilinx –vivado, Xilinx ISE, Synopsys, MATLAB, LT-Spice, DSCH, Hspice.

Coursework:

Introduction to CMOS Designing

Introduction to Microcontroller and Microprocessor

VLSI Design Principles

FPGA Designing with VHDL

Image Processing

Digital Logic Design

Digital Design with FPGA

Mixed Signal IC Design

Core Qualifications:

Proficient in operating the simulation and modeling equipment including the designing tools.

Extensive knowledge of the design concepts of VLSI/ASIC Design flow, analog circuit design and I/O circuit design.

Comprehensive knowledge of differential amps, CMOS Transistors, Filters.

Well acquainted with the basic characteristics of the digital designing instruments.

Result oriented with strong analytical, problem solving, and communication skills.

Self-driven and ability to work independently as well as in a team environment.

Professional Experience: September’13 - Feb’14

Title: VLSI Design Intern

Company Name: M Ram Technology Pvt. Ltd. Bangalore, India.

Designed and developed electronic components.

Performed unit level validation environment development, design schematic capture, floor planning, test plan, routing, and logic equivalency, circuit simulation, timing closure and test case implementation for the verification of design blocks

Implemented logic complex design blocks using RTL coding.

Executed the chip enhancement procedures including the procedures related to synthesis and time investigation.

Academic Projects:

Title: Design and Implementation of VGA controller November 2015

Purpose of this project was to design and implement VGA Controller on FPGA.

The VGA Controller program is written based on the block diagram using Verilog HDL.

Tools Used: Nexys2 Digilent FPGA board, Xilinx Vivado.

Title: Design of a Low Power SRAM August 2015

Implemented a 6T SRAM to overcome power consumption and a transient voltage boost on the word line to improve the write performance.

6T SRAM architecture is chosen for memory bit cell and an array is designed with that bit cell. Transient and parametric analyses were carried out in the simulation process and the power consumption is estimated.

Tools used: Layout editor, Cadence Virtuoso schematic editor, Hspice.

Title: Design of a Decoder January 2015

Designed a layout to perform 4:16 decode operation.

Both layout and schematic circuit of the decoder underwent DRC and then simulated through LVS to ensure they were identical. Results of the layout and schematic circuit were essentially identical and matched the theoretical results.

Tools Used: Cadence, LT spice, DSCH

Title: Design of a modern four way traffic light controller October 2014

Traffic Light sequence is generated using a specific switching mechanism which will help to control a traffic light system on a road in a specified sequence.

Coding was performed in Verilog and implemented the circuit on Programmable Logic Device.

Tools Used: Xilinx Vivado, Nexys2 Digilent FPGA, Schematic editor.

Title: Implementing Artificial Neural Networks using FPGA May 2013

The aim was to create and implement a technique of image compression using Artificial Neural Network

Implementation was done on FPGA for which the coding was done in Verilog.

Tools Used: MATLAB, Chipscope, Xilinx ISE.

Awards and Honors:

Attended State level Conference based on Advances in Electronics System Design.

Participated in Intercollege level for Design and debugging competition.

Attended workshop based on VLSI designing.

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