| Distance: | Job alert | Jobs 51 - 60 of 1677 |
Switch ASIC Design Engineer
Cornelis Networks
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Wayne, PA, 19087
... Implement RTL designs using Verilog/System Verilog for low-latency data paths, including Network-on-Chip (NoC) and crossbar designs. Define timing constraints for RTL blocks and collaborate with Physical Design engineers to optimize timing closure. ... - Aug 04
ASIC RTL/SoC Design Engineer
TetraMem INC
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Fremont, CA, 94537
... Qualifications MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design Experience with Verilog and system Verilog Experience with VCS, Verdi or other industry standard tools Experience with pre-layout ... - Aug 04
DDr5 verification design ENG
Current Openings
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Santa Clara, CA, 95053
... • Provide technical support to other teams PREFERRED EXPERIENCE: • Experience with C/C++ • Experience with Verilog, System Verilog, and modern verification libraries like UVM • 10+years of ASIC design verification experience • Experience / ... - Sep 01
ASIC Design Engineer - Packet Processing & Ethernet
Cornelis Networks
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Wayne, PA, 19087
... Implement RTL designs using Verilog/System Verilog for high-speed data paths and packet processing logic. Collaborate with verification engineers to create block- and system-level test plans to ensure comprehensive design coverage. Define timing ... - Aug 05
Staff Engineer, RTL
Ambiq Micro, Inc
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Austin, TX, 78730
... RTL development for IPs and SOCs using Verilog 3rd party IP identification, selection, and integration Collaboration with verification and FPGA teams in test plan development and debug Collaborate with the Physical Design team to close the design on ... - Sep 02
Performance Modeling/Verification Engineer - Intermediate (US)
ObjectWin Technology
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Santa Clara, CA, 95053
... Experience in Verilog/SystemVerilog/SystemC, preferred; Experience in C/Verilog environment using DPI/PLI, preferred; Strong analytical skills and attention to detail; Excellent written and communication skills; PCIe & AXI Knowledge Preferred - Aug 28
STA Engineer
Apolis
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San Jose, CA
... Synopsys DC/DCG/FC), Verilog/System Verilog programming Preferred Qualifications Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence) Experience with ... - Sep 01
ASIC Design Engineer
Apple
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Cupertino, CA
$151,091 - $220,900/yr
... Write tools, such as Clock Domain Crossing (CDC), Reset Domain Crossing (RDC) and Verilog RTL and Gate Linting to automate RTL generation and verifying RTL. Perform automation using Perl, Python and TCL to streamline processes for generating RTL and ... - Aug 27
DFT Engineer
Rivos
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American Canyon, CA, 94503
... of DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump Knowledge of Verilog and experience with simulators and waveform debugging tools Knowledge of Verilog / SystemVerilog Knowledge of Python,, ... - Aug 04
FPGA Design Engineer
microTECH Global Ltd
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Brentwood, Essex, CM13 2DP, United Kingdom
... Main Responsibilities: Design, develop, and verify FPGA modules in Verilog/SystemVerilog and VHDL Translate novel functional computing models into optimised RTL architectures Implement high:throughput, pipelined digital logic and memory interfaces ... - Aug 21